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Phung M Chung

CEO of Nexstgo

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Edits on 3 May, 2022
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Nexstgo
Edits on 15 Dec, 2021
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edited on 15 Dec, 2021
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Patent primary examiner of
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US Patent 11169874 Memory system including field programmable gate array (FPGA) and method of operating same
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US Patent 11175988 Memory storage device and data access method
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US Patent 11177830 Method and apparatus for data decoding in communication or broadcasting system
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US Patent 7328381 Testing system and method for memory modules having a memory hub architecture
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US Patent 7334170 Method for resolving parameters of DRAM
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US Patent 7334178 Randomized self-checking test system
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US Patent 7343547 Semiconductor integrated circuit, and semiconductor system including that semiconductor integrated circuit
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US Patent 7346825 Error method, system and medium
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US Patent 7356745 IC with parallel scan paths and compare circuitry
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US Patent 7360126 Method of and apparatus for managing disc defects using temporary defect management information (TDFL) and temporary defect management information (TDDS), and disc having the TDFL and TDDS
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US Patent 7360134 Centralized BIST engine for testing on-chip memory structures
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US Patent 7363553 System and method for adjusting soft decision thresholds in a soft-decision error correction system
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US Patent 7363558 Semiconductor device and method for testing the same
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US Patent 7363565 Method of testing apparatus having master logic unit and slave logic unit
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US Patent 7370250 Test patterns to insure read signal integrity for high speed DDR DRAM
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US Patent 7370252 Interleaving apparatus and method for orthogonal frequency division multiplexing transmitter
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US Patent 7370255 Circuit testing with ring-connected test instrument modules
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US Patent 7373563 Root cause correlation in connectionless networks
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US Patent 7380191 ABIST data compression and serialization for memory built-in self test of SRAM with redundancy
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US Patent 7380194 Data processing method and apparatus, recording medium, reproducing method and apparatus
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US Patent 7383492 First-in/first-out (FIFO) information protection and error detection method and apparatus
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US Patent 7386779 Systems and methods for correcting errors in a received frame
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US Patent 7389453 Queuing methods for distributing programs for producing test data
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US Patent 7395479 Over-voltage test for automatic test equipment
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US Patent 7395487 Common circuitry supporting both bit node and check node processing in LDPC (Low Density Parity Check) decoder
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US Patent 7398441 System and method for providing secure boundary scan interface access
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US Patent 7401272 Apparatus and method for high speed sampling or testing of data signals using automated testing equipment
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US Patent 7401276 Semiconductor device with test circuit and test method of the same
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US Patent 7401277 Semiconductor integrated circuit and scan test method therefor
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US Patent 7401284 Module for generating circuits for decoding convolutional codes, related method and circuit
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US Patent 7406641 Selective control of test-access ports in integrated circuits
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US Patent 7409615 Test apparatus and test method
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US Patent 7409618 Self verifying communications testing
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US Patent 7409620 Simplified high speed test system
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US Patent 7409631 Error-detection flip-flop
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US Patent 7418640 Dynamically reconfigurable shared scan-in test architecture
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US Patent 7418642 Built-in-self-test using embedded memory and processor in an application specific integrated circuit
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US Patent 7421631 Semiconductor device with termination resistor circuit
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US Patent 7424652 Method and apparatus for detection of transmission unit loss and/or replication
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US Patent 7424657 Method and device for testing an integrated circuit, integrated circuit to be tested, and wafer with a large number of integrated circuits to be tested
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US Patent 7428670 Apparatus for managing disc defects using temporary defect management information and temporary defect management information, and disc having the temporary defect management information and temporary defect management information
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US Patent 7428673 Test method for determining the wire configuration for circuit carriers with components arranged thereon
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US Patent 7428676 Boundary scan device
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US Patent 7434113 Method of analyzing serial data streams
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US Patent 7434116 Unitary testing apparatus for performing bit error rate measurements on optical components
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US Patent 7434119 Method and apparatus for memory self testing
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US Patent 7434122 Flash memory device for performing bad block management and method of performing bad block management of flash memory device
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US Patent 7437624 Method and apparatus for analyzing serial data streams
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US Patent 7437653 Erased sector detection mechanisms
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US Patent 7441166 Testing apparatus and testing method
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US Patent 7444559 Generation of memory test patterns for DLL calibration
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US Patent 7444561 Verifier for remotely verifying integrity of memory and method thereof
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US Patent 7444575 Architecture and method for testing of an integrated circuit device
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US Patent 7444580 System and method for interleaving data in a communication device
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US Patent 7447951 Information storage medium, method of managing replacement information, recording/reproducing apparatus, and host apparatus
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US Patent 7447952 Method of and apparatus for managing disc defects using temporary defect management information (TDFL) and temporary defect management information (TDDS), and disc having the TDFL and TDDS
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US Patent 7447959 Semiconductor integrated circuit and a method of testing the same
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US Patent 7447967 MIMO hybrid-ARQ using basis hopping
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US Patent 7451373 Circuit for compression and storage of circuit diagnosis data
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US Patent 7451383 Rate matching device and method for a data communication system
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US Patent 7454670 Data management apparatus and method of flash memory
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US Patent 7457998 Scan register and methods of using the same
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US Patent 7457999 Debug port system for control and observation
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US Patent 7464306 Status of overall health of nonvolatile memory
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US Patent 7464307 High performance serial bus testing methodology
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US Patent 7467336 Method and apparatus to measure and display data dependent eye diagrams
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US Patent 7467338 Apparatus and method for generating an error signal
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US Patent 7467339 Semiconductor integrated circuit and a method of testing the same
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US Patent 7467340 TAP, ST, lockout, and IR SO enable output data control
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US Patent 7472321 Test apparatus for mixed-signal semiconductor device
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US Patent 7475309 Parallel test mode for multi-core processors
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US Patent 7478290 Testing DRAM chips with a PC motherboard attached to a chip handler by a solder-side adaptor board with an advanced-memory buffer (AMB)
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US Patent 7478296 Continuous application and decompression of test patterns to a circuit-under-test
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US Patent 7480843 Configuration access from a boundary-scannable device
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US Patent 7484145 Method for embedded integrated end-to-end testing
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US Patent 7487430 Apparatus and method for receiving packet data control channel in a mobile communication system
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US Patent 7490276 Testing self-repairing memory of a device
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US Patent 7493540 Continuous application and decompression of test patterns to a circuit-under-test
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US Patent 7496806 Method of and apparatus for managing disc defects using temporary defect management information (TDFL) and temporary defect management information (TDDS), and disc having the TDFL and TDDS
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US Patent 7502978 Systems and methods for reconfiguring scan chains
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US Patent 7502992 Method and apparatus for detecting presence of errors in data transmitted between components in a data storage system using an I2C protocol
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US Patent 7506229 Method and system for optimizing an integrated circuit
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US Patent 7506240 Method and apparatus for image processing
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US Patent 7509544 Data repair and synchronization method of dual flash read only memory
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US Patent 7509548 Method and apparatus for integrated circuit self-description
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US Patent 7509549 Dynamic frequency scaling for JTAG communication
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US Patent 7509552 Multi-thread parallel segment scan simulation of chip element performance
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US Patent 7509566 Flash memory
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US Patent 7509567 System and method for resolving data inconsistencies with a data majority
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US Patent 7516377 System and method for testing an on-chip initialization counter circuit
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US Patent 11190218 Code rate switching mechanism for data storage system
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US Patent 7519872 Deinterleaving device for digital broadcast receivers having a downsized deinterleaver memory and deinterleaving method thereof
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US Patent 7519875 Method and apparatus for enabling a user to determine whether a defective location in a memory device has been remapped to a redundant memory portion
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US Patent 7519882 Intelligent binning for electrically repairable semiconductor chips
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US Patent 7519887 Apparatus for storing and formatting data
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US Patent 7526709 Error detection and correction in a CAM
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US Patent 7539929 Error correction for data communication
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US Patent 7543207 Full scan solution for latched-based design
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US Patent 7546499 Communication signal testing with a programmable logic device
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US Patent 7546503 Selecting between tap/scan with instructions and lock out signal
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US Patent 7546505 Built in self test transport controller architecture
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US Patent 7546506 DRAM stacked package, DIMM, and semiconductor manufacturing method
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US Patent 7549098 Redundancy programming for a memory device
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US Patent 7552366 Jitter tolerance testing apparatus, systems, and methods
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US Patent 7559002 Multi-thread parallel segment scan simulation of chip element performance
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US Patent 7559003 Semiconductor memory test apparatus
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US Patent 7568134 Method of exhaustively testing an embedded ROM using generated ATPG test patterns
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US Patent 7568139 Process for identifying the location of a break in a scan chain in real time
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US Patent 7571359 Clock distribution circuits and methods of operating same that use multiple clock circuits connected by phase detector circuits to generate and synchronize local clock signals
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US Patent 7574638 Semiconductor device tested using minimum pins and methods of testing the same
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US Patent 7574640 Compacting circuit responses
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US Patent 7577888 Self learning signatures
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US Patent 7581146 Semiconductor memory device storing repair information avoiding memory cell of fail bit operating method thereof
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US Patent 7581147 Radio resource control-service data unit reception
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US Patent 7584391 Smart verify for multi-state memories
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US Patent 7584392 Test compaction using linear-matrix driven scan chains
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US Patent 7584404 Method and apparatus for multimedia communication over packet channels
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US Patent 7587642 System and method for performing concurrent mixed signal testing on a single processor
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US Patent 7594156 High-efficiency compact turbo-decoder
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US Patent 7596733 Dynamically reconfigurable shared scan-in test architecture
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US Patent 7603594 Wireless communications system
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US Patent 7610522 Compliance of master-slave modes for low-level debug of serial links
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US Patent 7613963 Wireless method and apparatus for testing armament circuits
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US Patent 7613964 Relay device and corresponding method
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US Patent 7617424 Error monitoring for serial links
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US Patent 7617427 Method and apparatus for detecting defects in integrated circuit die from stimulation of statistical outlier signatures
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US Patent 7627796 Testing method for permanent electrical removal of an integrated circuit output
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US Patent 7627797 Test access port
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US Patent 7631232 Parallel burning system and method
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US Patent 7634693 Method and apparatus for analyzing serial data streams
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US Patent 7634695 Test apparatus and selection apparatus
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US Patent 7634713 Error detection and location circuitry for configuration random-access memory
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US Patent 7636876 Cost-based performance driven legalization technique for placement in logic designs
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US Patent 7640472 Serialization of hardware and software debug data
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US Patent 7640473 Semiconductor integrated circuit apparatus and control method thereof
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US Patent 7644332 Integrated circuit and method for identifying propagation time errors in integrated circuits
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US Patent 7647535 Using a delay clock to optimize the timing margin of sequential logic
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US Patent 7650546 Flexible JTAG architecture
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US Patent 7653843 Method and arrangement to estimate transmission channel characteristics
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US Patent 7653850 Delay fault detection using latch with error sampling
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US Patent 7669092 Apparatus, method, and system of NAND defect management
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US Patent 7669093 Information radio transmission system
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US Patent 7669095 Methods and apparatus for error injection
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US Patent 7673196 Methods and apparatus for communicating with a target circuit
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US Patent 7673199 Multi-stream interface for parallel test processing
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US Patent 7673200 Reprogrammable built-in-self-test integrated circuit and test method for the same
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US Patent 7676714 Extender strip and test assembly for testing memory card operation
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US Patent 7676715 Integrated circuit with continuous testing of repetitive functional blocks
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US Patent 7681090 Ripple correlation control based on limited sampling
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US Patent 7681098 Systems and methods for improved fault coverage of LBIST testing
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US Patent 7681099 Techniques for integrated circuit clock signal manipulation to facilitate functional and speed test
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US Patent 7685478 Method of testing memory card operation
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US Patent 7689885 Integrated circuit and method for identifying propagation time errors in integrated circuits
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US Patent 7694193 Systems and methods for implementing a stride value for accessing memory
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US Patent 7694202 Providing memory test patterns for DLL calibration
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US Patent 7694211 Method and apparatus for error compensation
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US Patent 7698609 Process measuring device with expanded hardware error detection
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US Patent 7698616 MIMO Hybrid-ARQ using basis hopping
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US Patent 7702978 Soft error location and sensitivity detection for programmable devices
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US Patent 7702979 Semiconductor integrated circuit incorporating test configuration and test method for the same
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US Patent 7702984 High volume testing for USB electronic data flash cards
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US Patent 7716540 Standalone data storage device electromagnetic interference test setup and procedure
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US Patent 7716545 Semiconductor integrated circuit and method for controlling the same
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US Patent 7716547 Circuit for compression and storage of circuit diagnosis data
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US Patent 7721165 External storage device and memory access control method thereof
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US Patent 7725790 Selectable dual mode test access port method and apparatus
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US Patent 7725795 Load generating apparatus and load testing method
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US Patent 7730370 Apparatus and method for disk read checking
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US Patent 7734965 Methods, architectures, circuits and systems for transmission error determination
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US Patent 7734971 Scan output connection in tap and scan test port
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US Patent 7739559 Semiconductor device and program data redundancy method therefor
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US Patent 7743290 Status of overall health of nonvolatile memory
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US Patent 7743298 Methods and apparatus for scan testing of integrated circuits with scan registers
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US Patent 7743299 Dynamically reconfigurable shared scan-in test architecture
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US Patent 7743303 Defective memory block remapping method and system, and memory device and processor-based system using same
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US Patent 7747911 Self verification of non-volatile memory
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US Patent 7747920 Method and apparatus for unifying self-test with scan-test during prototype debug and production test
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US Patent 7747922 Adaptive hybrid ARQ systems with BCJR decoding
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US Patent 7747927 Method for adapting a memory system to operate with a legacy host originally designed to operate with a different memory system
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US Patent 7752516 Semiconductor device and scan test method
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US Patent 7757132 Memory with an output register for test data and process for testing a memory and memory module
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US Patent RE41497 Radio transmission method and radio transmission device
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US Patent 7774663 Dynamically reconfigurable shared scan-in test architecture
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US Patent 7779331 Systems and methods for tri-column code based error reduction
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US Patent 7783945 Display apparatus and test circuit thereof
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US Patent 7788553 Mass production testing of USB flash cards with various flash memory cells
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US Patent 7788565 Semiconductor integrated circuit
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US Patent 7788573 Fault detection method, test circuit and semiconductor device
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US Patent 7793176 Method of increasing path coverage in transition test generation
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US Patent 7793181 Sequential storage circuitry for an integrated circuit
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US Patent 7793183 Microcomputer and method of testing the same
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US Patent 7797590 Consensus testing of electronic system
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US Patent 7797592 Automatic communication channel fault mitigation
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US Patent 7805648 Shift-frequency scaling
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US Patent 7805657 Techniques to determine transmission quality of a signal propagation medium
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US Patent 7810004 Integrated circuit having a subordinate test interface
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US Patent 7814378 Verification of memory consistency and transactional memory
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US Patent 7814381 Semiconductor memory device
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US Patent 7823032 Data recording/reproduction for write-once discs
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US Patent 7827450 Defect detection and handling for memory based on pilot cells
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US Patent 7836367 Dynamically reconfigurable shared scan-in test architecture
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US Patent 7836368 Dynamically reconfigurable shared scan-in test architecture
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US Patent 7844868 System and method for implementing a stride value for memory testing
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US Patent 7844870 Method for embedded integrated end-to-end testing
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US Patent 7849371 Time lag measuring device, distance measuring apparatus and distance measuring method
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US Patent 7853823 System and method for reconstructing lost data in a storage system
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US Patent 7853839 Method and apparatus for verifying the correctness of FTAP data packets received on the FLO waveform
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US Patent 7853849 High-speed serial transfer device test method, program, and device
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US Patent 7870453 Circuit arrangement and method of testing an application circuit provided in said circuit arrangement
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US Patent 7873885 SSD test systems and methods
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US Patent 7877650 Core circuit test architecture
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US Patent 7877651 Dual mode test access port method and apparatus
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US Patent 7877656 Continuous application and decompression of test patterns to a circuit-under-test
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US Patent 7886203 Method and apparatus for bit interleaving and deinterleaving in wireless communication systems
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US Patent 7890818 Read level control apparatuses and methods
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US Patent 7890828 Built-in self-test using embedded memory and processor in an application specific integrated circuit
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US Patent 7895483 Software memory leak analysis using memory isolation
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US Patent 7900105 Dynamically reconfigurable shared scan-in test architecture
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US Patent 7908529 Flash memory
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US Patent 7913129 Method of testing data paths in an electronic circuit
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US Patent RE42264 Field programmable device
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US Patent 7921344 Multi-stage data processor with signal repeater
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US Patent 7925936 Memory device with non-uniform programming levels
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US Patent 7925941 Test compaction using linear-matrix driven scan chains
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US Patent 7925959 Systems and methods for tri-column code based error reduction
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US Patent 7937630 Semiconductor memory and method for testing the same
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US Patent 7941718 Electronic device testing system
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US Patent 7945821 Time lag measuring device, distance measuring apparatus and distance measuring method
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US Patent 7945828 Integrated circuit arrangement and design method
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US Patent 7945830 Method and apparatus for unifying self-test with scan-test during prototype debug and production test
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US Patent 7949918 Asynchronous communication using standard boundary architecture cells
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US Patent 7954019 Flash storage device and method and system for testing the same
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US Patent 7954020 Method and apparatus for testing a circuit
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US Patent 7954024 Selecting scan test/TAP with FF receiving lock in and update-IR
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US Patent 7954028 Structure for redundancy programming of a memory device
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US Patent 7958417 Apparatus and method for isolating portions of a scan path of a system-on-chip
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US Patent 7958419 Entering a shift-DR state in one of star connected components
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US Patent 7958431 Method for interleaving data in a communication device
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US Patent 7958439 Defective memory block remapping method and system, and memory device and processor-based system using same
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US Patent 7962806 Method and system for providing bit error rate characterization
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US Patent 7966538 Microprocessor and method for detecting faults therein
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US Patent 7971092 Methods and devices for high performance consistency check
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US Patent 7971108 Modem-assisted bit error concealment for audio communications systems
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US Patent 7971114 Method for testing a memory device
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US Patent 7971117 Test circuits of semiconductor memory device for multi-chip testing and method for testing multi chips
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US Patent 7975194 System and method for adaptive nonlinear test vector compression
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US Patent 7979758 Semiconductor memory device
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US Patent 7987395 Evaluation method of random error distribution and evaluation apparatus thereof
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US Patent 7992060 Apparatus, methods, and system of NAND defect management
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US Patent 7992077 Data slicer having an error correction device
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US Patent 8001434 Memory board with self-testing capability
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US Patent 8001437 Test pattern generation method for avoiding false testing in two-pattern testing for semiconductor integrated circuit
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US Patent 8001443 Data storage apparatus, data storage controller, and related automated testing method
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US Patent 8006145 Semiconductor integrated circuit device
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US Patent 8010852 Defect detection and handling for memory based on pilot cells
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US Patent 8010864 Parameter setting with error correction for analog circuits
Edits on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
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US Patent 8010864 Parameter setting with error correction for analog circuits
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Golden AI
edited on 8 Dec, 2021
Edits made to:
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Patent primary examiner of
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US Patent 8010852 Defect detection and handling for memory based on pilot cells
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Golden AI
edited on 8 Dec, 2021
Edits made to:
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Patent primary examiner of
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US Patent 8006145 Semiconductor integrated circuit device
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Golden AI
edited on 8 Dec, 2021
Edits made to:
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Patent primary examiner of
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US Patent 8001443 Data storage apparatus, data storage controller, and related automated testing method
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Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
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Patent primary examiner of
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US Patent 8001434 Memory board with self-testing capability
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7992077 Data slicer having an error correction device
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7992060 Apparatus, methods, and system of NAND defect management
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
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Patent primary examiner of
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US Patent 7987395 Evaluation method of random error distribution and evaluation apparatus thereof
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
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Patent primary examiner of
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US Patent 7979758 Semiconductor memory device
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7975194 System and method for adaptive nonlinear test vector compression
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Golden AI
edited on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
Edits made to:
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Patent primary examiner of
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US Patent 7971108 Modem-assisted bit error concealment for audio communications systems
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Golden AI
edited on 8 Dec, 2021
Edits made to:
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Patent primary examiner of
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US Patent 7971114 Method for testing a memory device
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Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
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US Patent 7971092 Methods and devices for high performance consistency check
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Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
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US Patent 7966538 Microprocessor and method for detecting faults therein
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Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
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US Patent 7962806 Method and system for providing bit error rate characterization
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Golden AI
edited on 7 Dec, 2021

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