SBIR/STTR Award attributes
Pacific Microchip Corp. proposes to design a 28GHz spectrometer ASIC which performs channelizing the signal#39;s spectrum. The ASIC includes an 8-bit 56GS/s time-interleaved ADC coupled with a digital backend performing digital poly-phase filter function and parallelized Fast Fourier Transform (FFT). To achieve 28GHz signal bandwidth, we will apply a time-interleaved temporal ADC architecture with advanced minimization of the time-interleaving related parameter mismatches in subADCs. This is expected to result in significant reduction of unwanted artifacts in the output spectrum. The feasibility of implementation of the ADC based on a charge ramping quantizer was already proven within another SBIR project. Instead of overdesigning, when seeking to maximize the performance, the ADC will rely on comprehensive calibration of ADC parameters. On-chip phase locked loops (PLLs) will be used for clock synthesis. For convenient interfacing with field programmable gate arrays (FPGAs), the ASIC will include a high-speed JESD204B standard data interface. Phase I work will provide the proof of ASIC feasibility ndash; critical blocks will be implemented and verified at targeted technology node. In Phase II, a silicon proven spectrometer ASIC will be fabricated and tested.
