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Naum B Levin

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Edits on 14 Dec, 2021
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Golden AI
edited on 14 Dec, 2021
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Infobox (-129 properties)
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Patent primary examiner of
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US Patent 7418686 System for representing the logical and physical information of an integrated circuit
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US Patent 7487475 Systems, methods, and apparatus to perform statistical static timing analysis
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US Patent 7487571 Control adjustable device configurations to induce parameter variations to control parameter skews
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US Patent 7500205 Skew reduction for generated clocks
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US Patent 7506284 Event driven switch level simulation method and simulator
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US Patent 7506293 Characterizing sequential cells using interdependent setup and hold times, and utilizing the sequential cell characterizations in static timing analysis
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US Patent 7506297 Methodology for scheduling, partitioning and mapping computational tasks onto scalable, high performance, hybrid FPGA networks
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US Patent 7546561 System and method of state point correspondence with constrained function determination
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US Patent 7562326 Method of generating a standard cell layout and transferring the standard cell layout to a substrate
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US Patent 7562327 Mask layout design improvement in gate width direction
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US Patent 7562333 Method and process for generating an optical proximity correction model based on layout density
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US Patent 7562336 Contrast based resolution enhancement for photolithographic processing
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US Patent 7565632 Behavioral synthesizer system, operation synthesizing method and program
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US Patent 7571400 Chip design verifying and chip testing apparatus and method
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US Patent 7571402 Scan chain modification for reduced leakage
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US Patent 7571405 Electrical design rule checking expert traverser system
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US Patent 7571406 Clock tree adjustable buffer
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US Patent 7571407 Semiconductor integrated circuit and method of testing delay thereof
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US Patent 7571408 Methods and apparatus for diagonal route shielding
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US Patent 7571410 Resonant tree driven clock distribution grid
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US Patent 7571412 Method and system for semiconductor device characterization pattern generation and analysis
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US Patent 7571423 Optimized photomasks for photolithography
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US Patent 7571424 Diffused aerial image model semiconductor device fabrication
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US Patent 7581199 Use of state nodes for efficient simulation of large digital circuits at the transistor level
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US Patent 7584450 Method and apparatus for using a database to quickly identify and correct a manufacturing problem area in a layout
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US Patent 7587695 Protection boundaries in a parallel printed circuit board design environment
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US Patent 7587700 Process monitoring system and method for processing a large number of sub-micron measurement targets
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US Patent 7590962 Design method and architecture for power gate switch placement
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US Patent 7603646 Method and apparatus for power optimization using don't care conditions of configuration bits in lookup tables
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US Patent 7607116 Method and apparatus for verifying system-on-chip model
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US Patent 7614024 Method to implement metal fill during integrated circuit design and layout
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US Patent 7614031 Drawing apparatus with drawing data correction function
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US Patent 7617465 Method and mechanism for performing latch-up check on an IC design
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US Patent 7620931 Method of adding fabrication monitors to integrated circuit chips
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US Patent 7624362 Circuit analysis device using processor information
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US Patent 7631281 Method for modeling varactor by direct extraction of parameters
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US Patent 7634749 Skew insensitive clocking method and apparatus
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US Patent 7634751 Replacing single-cut via into multi-cut via in semiconductor integrated circuit design
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US Patent 7634752 System and method for design entry and synthesis in programmable logic devices
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US Patent 7636907 Balancing logic resource usage in a programmable integrated circuit
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US Patent 7640529 User-friendly rule-based system and method for automatically generating photomask orders
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US Patent 7657855 Efficient timing graph update for dynamic netlist changes
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US Patent 7657864 System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques
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US Patent 7661084 Implementing memory read data eye stretcher
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US Patent 7665055 Semiconductor apparatus design method in which dummy line is placed in close proximity to signal line
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US Patent 7665057 Method for calculating optimal length of trace between adjoining bends and computer accessible storage media
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US Patent 7669167 Rule based system and method for automatically generating photomask orders by conditioning information from a customer's computer system
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US Patent 7669172 Pattern creation method, mask manufacturing method and semiconductor device manufacturing method
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US Patent 7673259 System and method for synthesis reuse
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US Patent 7681159 System and method for detecting defects in a semiconductor during manufacturing thereof
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US Patent 7685541 Translation of high-level circuit design blocks into hardware description language
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US Patent 7689940 Method and apparatus for allocating data paths
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US Patent 7689960 Programmable via modeling
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US Patent 7694242 System and method of replacing flip-flops with pulsed latches in circuit designs
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US Patent 7694243 Avoiding device stressing
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US Patent 7694250 Method for design and verification of safety critical systems
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US Patent 7694266 Method and apparatus for dynamic frequency voltage switching circuit synthesis
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US Patent 7703056 Circuit designing program and circuit designing system having function of test point insertion
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US Patent 7703063 Implementing memory read data eye stretcher
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US Patent 7707527 Huygens' box methodology for signal integrity analysis
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US Patent 7707533 Data-mining-based knowledge extraction and visualization of analog/mixed-signal/custom digital circuit design flow
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US Patent 7707539 Facilitating process model accuracy by modeling mask corner rounding effects
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US Patent 7721248 Circuit element function matching despite auto-generated dummy shapes
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US Patent 7725844 Method and circuit for implementing eFuse sense amplifier verification
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US Patent 7730435 Automatic test component generation and inclusion into simulation testbench
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US Patent 7735045 Method and apparatus for mapping flip-flop logic onto shift register logic
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US Patent 7739643 Crosstalk noise reduction circuit and method
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US Patent 7743355 Method of achieving timing closure in digital integrated circuits by optimizing individual macros
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US Patent 7747978 System and method for creating a focus-exposure model of a lithography process
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US Patent 7752591 Board layout check apparatus and board layout check method for guard wiring
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US Patent 7752595 Method for verifying and correcting post-OPC pattern layout
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US Patent 7757197 Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device
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US Patent 7761835 Semiconductor device design method, semiconductor device design system, and computer program for extracting parasitic parameters
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US Patent 7765505 Design rule management method, design rule management program, rule management apparatus and rule verification apparatus
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US Patent 7765508 Method and system for generating multiple implementation views of an IC design
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US Patent 7765510 Method of searching for wiring route including vias in integrated circuit
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US Patent 7765512 Relocatable circuit implemented in a programmable logic device
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US Patent 7765517 Method and apparatus for removing dummy features from a data structure
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US Patent 7765518 System and method for implementing optical rule checking to identify and quantify corner rounding errors
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US Patent 7774725 Computationally efficient modeling and simulation of large scale systems
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US Patent 7774733 Method and apparatus for user interface in home network and electronic device and storage medium therefor
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US Patent 7774734 Enhanced reach-based graph processing using shortcuts
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US Patent 7784010 Automatic routing system with variable width interconnect
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US Patent 7788618 Scalable dependent state element identification
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US Patent 7788624 Methods of balancing logic resource usage in a programmable logic device
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US Patent 7793237 System, structure and method of providing dynamic optimization of integrated circuits using a non-contact method of selection, and a design structure
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US Patent 7793238 Method and apparatus for improving a circuit layout using a hierarchical layout description
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US Patent 7793248 Method and apparatus for parameterizing hardware description language code in a system level design environment
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US Patent 7797652 Implementing integrated circuit yield estimation using voronoi diagrams
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US Patent 7802225 Optical proximity correction method, optical proximity correction apparatus, and optical proximity correction program, method of manufacturing semiconductor device, design rule formulating method, and optical proximity correction condition calculating method
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US Patent 7805693 IC chip design modeling using perimeter density to electrical characteristic correlation
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US Patent 7814441 System and method for identifying original design intents using 3D scan data
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US Patent 7818698 Accurate parasitic capacitance extraction for ultra large scale integrated circuits
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US Patent 7818708 Method and system for developing post-layout electronic data automation (EDA) applications
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US Patent 7823106 Variable performance ranking and modification in design for manufacturability of circuits
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US Patent 7823117 Separating a high-level programming language program into hardware and software components
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US Patent 7823118 Computer readable medium having multiple instructions stored in a computer readable device
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US Patent 7836422 System, method and apparatus for optimizing multiple wire pitches in integrated circuit design
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US Patent 7840924 Apparatus, method, and program for verifying logic circuit operating with multiple clock signals
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US Patent 7844927 Method for quality assured semiconductor device modeling
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US Patent 7849432 Shallow trench isolation dummy pattern and layout method using the same
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US Patent 7849435 Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits
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US Patent 7853919 Modeling mask corner rounding effects using multiple mask layers
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US Patent 7856608 Method and apparatus for generating current source noise model for creating semiconductor device model used in power supply noise analysis
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US Patent 7865856 System and method for performing transistor-level static performance analysis using cell-level static analysis tools
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US Patent 7873927 Partitioning a large design across multiple devices
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US Patent 7877715 Method and apparatus to use physical design information to detect IR drop prone test patterns
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US Patent 7882453 Semiconductor device metal programmable pooling and dies
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US Patent 7882455 Circuit and method using distributed phase change elements for across-chip temperature profiling
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US Patent 7882460 Method of circuit power tuning through post-process flattening
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US Patent 7882461 Method for optimized automatic clock gating
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US Patent 7882467 Test pattern evaluation method and test pattern evaluation device
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US Patent 7886245 Structure for optimizing the signal time behavior of an electronic circuit design
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US Patent 7886247 Method and apparatus for statistical path selection for at-speed testing
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US Patent 7886257 Methods for hierarchical noise analysis
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US Patent 7886258 Method and apparatus for removing dummy features from a data structure
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US Patent 7890895 Determination of values of physical parameters of one or several components of an electronic circuit or of a microelectro-mechanical system
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US Patent 7890900 Various methods and apparatuses for effective yield enhancement of good chip dies having memories per wafer
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US Patent 7890914 Layout data reduction for use with electronic design automation tools
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US Patent 7895538 System and method for providing a common instruction table
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US Patent 7895544 Method to graphically identify registers with unbalanced slack as part of placement driven synthesis optimization
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US Patent 7895547 Test pattern based process model calibration
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US Patent 7895559 Method for designing structured ASICs in silicon processes with three unique masking steps
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US Patent 7904859 Method and apparatus for determining a phase relationship between asynchronous clock signals
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US Patent 7904860 Method and apparatus for selecting programmable interconnects to reduce clock skew
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US Patent 7913199 Structure for a duty cycle correction circuit
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US Patent 7913201 Structure for estimating power consumption of integrated circuitry
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US Patent 7917871 Method and program for pattern data generation using a modification guide
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US Patent 7917875 Clock tree adjustable buffer
Edits on 7 Dec, 2021
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Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7917875 Clock tree adjustable buffer
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Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7917871 Method and program for pattern data generation using a modification guide
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7913201 Structure for estimating power consumption of integrated circuitry
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7913199 Structure for a duty cycle correction circuit
Edits on 7 Dec, 2021
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7904860 Method and apparatus for selecting programmable interconnects to reduce clock skew
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Golden AI
edited on 7 Dec, 2021
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7895538 System and method for providing a common instruction table
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7895547 Test pattern based process model calibration
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Golden AI
edited on 7 Dec, 2021
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Golden AI
edited on 6 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7890914 Layout data reduction for use with electronic design automation tools
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Golden AI
edited on 6 Dec, 2021
Golden AI profile picture
Golden AI
edited on 6 Dec, 2021
Golden AI profile picture
Golden AI
edited on 6 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7886258 Method and apparatus for removing dummy features from a data structure
Golden AI profile picture
Golden AI
edited on 6 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7886257 Methods for hierarchical noise analysis
Golden AI profile picture
Golden AI
edited on 6 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7886247 Method and apparatus for statistical path selection for at-speed testing
Golden AI profile picture
Golden AI
edited on 6 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7886245 Structure for optimizing the signal time behavior of an electronic circuit design
Golden AI profile picture
Golden AI
edited on 6 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7882467 Test pattern evaluation method and test pattern evaluation device
Golden AI profile picture
Golden AI
edited on 6 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7882461 Method for optimized automatic clock gating

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