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Mano Padmanabhan

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Edits on 14 Dec, 2021
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edited on 14 Dec, 2021
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Patent primary examiner of
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US Patent 7089361 Dynamic allocation of shared cache directory for optimizing performance
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US Patent 7089363 System and method for inline invalidation of cached data
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US Patent 7089367 Reducing memory access latencies from a bus using pre-fetching and caching
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US Patent 7089373 Shadow register to enhance lock acquisition
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US Patent 7089376 Reducing snoop response time for snoopers without copies of requested data via snoop filtering
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US Patent 7089377 Virtualization system for computers with a region-based memory architecture
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US Patent 7089400 Data speculation based on stack-relative addressing patterns
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US Patent 7093062 Flash memory data bus for synchronous burst read page
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US Patent 7093072 Methods for improved data caching
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US Patent 7093073 Systems and methods for adjusting caching policies for web service requests
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US Patent 7093076 Memory system having two-way ring topology and memory device and memory module for ring-topology memory system
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US Patent 7093090 Method for creating a virtual data copy of a volume being restored
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US Patent 7093091 Selectable block protection for non-volatile memory
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US Patent 7093102 Code sequence for vector gather and scatter
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US Patent 7096311 Updating electronic files using byte-level file differencing and updating algorithms
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US Patent 7096319 Cache memory managing method for computer system
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US Patent 7096321 Method and system for a cache replacement technique with adaptive skipping
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US Patent 7096337 Disk storage accessing system and method for changing access path to storage devices
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US Patent 7096338 Storage system and data relocation control device
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US Patent 7096342 Flexible LUN/LBA interface for content addressable reference storage
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US Patent 7099989 System and technique to reduce cycle time by performing column redundancy checks during a delay to accommodate variations in timing of a data strobe signal
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US Patent 7099993 Multi-level caching in data storage devices
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US Patent 7100002 Port independent data transaction interface for multi-port devices
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US Patent 7100005 Record storage and retrieval solution
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US Patent 7100009 Method and system for selective memory coalescing across memory heap boundaries
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US Patent 7100013 Method and apparatus for partial memory power shutoff
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US Patent 7100015 Redirecting external memory allocation operations to an internal memory manager
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US Patent 7100017 Method and apparatus for performing distributed processing of program code
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US Patent 7103718 Non-volatile memory module for use in a computer system
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US Patent 7103743 System and method of accessing vital product data
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US Patent 7103748 Memory management for real-time applications
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US Patent 7103750 Method and apparatus for finding repeated substrings in pattern recognition
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US Patent 7107386 Memory bus arbitration using memory bank readiness
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US Patent 7107398 Changing a mode of a storage subsystem in a system
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US Patent 7107400 System, apparatus, and process for evaluating projected cache sizes
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US Patent 7107401 Method and circuit to combine cache and delay line memory
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US Patent 7111130 Coherency management for a “switchless” distributed shared memory computer system
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US Patent 7111142 System for quickly transferring data
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US Patent 7111145 TLB miss fault handler and method for accessing multiple page tables
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US Patent 7114025 Semiconductor memory having test function for refresh operation
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US Patent 7114035 Software-controlled cache set management with software-generated class identifiers
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US Patent 7114044 Storage system, method of controlling storage system, and storage device
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US Patent 7114052 Semiconductor memory device, a sector-address conversion circuit, an address-conversion method, and operation method of the semiconductor memory device
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US Patent 7114053 Virtual-to-physical address conversion in a secure system
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US Patent 7117302 Boot techniques involving tape media
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US Patent 7117305 Data storage system having cache memory manager
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US Patent 7117309 Method of detecting sequential workloads to increase host read throughput
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US Patent 7117311 Hot plug cache coherent interface method and apparatus
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US Patent 7117319 Managing processor architected state upon an interrupt
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US Patent 7117326 Tracking modifications to a memory
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US Patent 7117330 Synchronization techniques in a multithreaded environment
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US Patent 7117334 Dynamic node partitioning utilizing sleep state
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US Patent 7117336 Computer system for managing storage areas in a plurality of storage devices
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US Patent 7120727 Reconfigurable memory module and method
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US Patent 7120734 Signal processing circuit for optical disk player having a shared memory for both an anti-shock mechanism and a CD-ROM decoder
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US Patent 7120740 Disk array controller
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US Patent 7120743 Arbitration system and method for memory responses in a hub-based memory system
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US Patent 7120748 Software-controlled cache set management
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US Patent 7120759 Storage system and method for prestaging data in a cache for improved performance
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US Patent 7120771 Secure mode for processors supporting MMU
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US Patent 7120772 Micro-system for burn-in system program from a plug-able subsystem into main memory and method thereof
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US Patent 7120779 Address offset generation within a data processing system
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US Patent 7124236 Microprocessor including bank-pipelined cache with asynchronous data blocks
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US Patent 7124245 Data storage system having cache memory manager with packet switching network
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US Patent 7124246 Storage management method and system
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US Patent 7124247 Quantification of a virtual disk allocation pattern in a virtualized storage pool
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US Patent 7124250 Memory module device for use in high-frequency operation
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US Patent 7124264 Storage system, control method for storage system, and storage control unit
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US Patent 7124272 File usage history log for improved placement of files in differential rate memory according to frequency of utilizations and volatility of allocation space
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US Patent 7127557 RAID apparatus and logical device expansion method thereof
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US Patent 7127558 Virtualization controller, access path control method and computer system
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US Patent 7127581 Data-migration method
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US Patent 7127585 Storage having logical partitioning capability and systems which include the storage
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US Patent 7130936 System, methods, and computer program product for shared memory queue
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US Patent 7130956 Storage system including hierarchical cache metadata
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US Patent 7130967 Method and system for supplier-based memory speculation in a memory subsystem of a data processing system
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US Patent 7130976 Remote copy method and remote copy system to eliminate use of excess volume for copying data
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US Patent 7130977 Controlling access to a control register of a microprocessor
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US Patent 7130980 Use of a resource identifier to import a program from external memory for an overlay
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US Patent 7133975 Cache memory system including a cache memory employing a tag including associated touch bits
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US Patent 7133978 Method and apparatus for processing data stored in a memory shared among a plurality of processors
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US Patent 7133984 Method and system for migrating data
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US Patent 7133988 Method and apparatus for managing direct I/O to storage systems in virtualization
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US Patent 7133992 Burst counter controller and method in a memory device operable in a 2-bit prefetch mode
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US Patent 7133994 Configuration size determination in logically partitioned environment
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US Patent 7136962 Storage device controlling apparatus and a circuit board for the same
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US Patent 7136964 Disk array with spare logic drive created from spare physical drives
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US Patent 7136965 Microcomputer
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US Patent 7136969 Using the message fabric to maintain cache coherency of local caches of global memory
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US Patent 7136974 Systems and methods of data migration in snapshot operations
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US Patent 7139862 Interleaving method and apparatus with parallel access in linear and interleaved order
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US Patent 7139865 LIFO type data storage device incorporating two random access memories
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US Patent 7139885 Method and apparatus for managing storage based replication
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US Patent 7139888 Data processing system
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US Patent 7139894 System and methods for sharing configuration information with multiple processes via shared memory
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US Patent 7143229 Single-chip microcomputer with dynamic burn-in test function and dynamic burn-in testing method therefor
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US Patent 7143232 Method, system, and program for maintaining a directory for data written to a storage medium
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US Patent 7143240 System and method for providing a cost-adaptive cache
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US Patent 7143241 Cache management in a mobile device
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US Patent 7143242 Dynamic priority external transaction system
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US Patent 7143244 System and method for invalidating data in a hierarchy of caches
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US Patent 7143245 System and method for read migratory optimization in a cache coherency protocol
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US Patent 7143251 Data storage using identifiers
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US Patent 7143252 Storage apparatus system and method of data backup
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US Patent 7143260 Intermediate descriptions of intent for storage allocation
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US Patent 7146456 Memory device with a flexible reduced density option
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US Patent 7146467 Method of adaptive read cache pre-fetching to increase host read throughput
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US Patent 7146468 Cache memory and method for handling effects of external snoops colliding with in-flight operations internally to the cache
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US Patent 7146470 Real-time motor controller with additional down-up-loadable controller functionality
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US Patent 7146480 Configurable memory system
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US Patent 7146482 Memory mapped input/output emulation
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US Patent 7149841 Memory devices with buffered command address bus
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US Patent 7149852 System and method for blocking data responses
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US Patent 7149854 External locking mechanism for personal computer memory locations
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US Patent 7149857 Out of order DRAM sequencer
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US Patent 7149862 Access control in a data processing apparatus
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US Patent 7155562 Method for reading while writing to a single partition flash memory
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US Patent 7155563 Circuits to generate a sequential index for an input number in a pre-defined list of numbers
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US Patent 7155580 Information processing apparatus and method of controlling memory thereof
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US Patent 7155583 Memory management system and method for a mobile device
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US Patent 7155593 Method for managing volume groups considering storage tiers
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US Patent 7155594 Method, computer system, and relay device for data transfer among plural memories to reduce the number of memory devices with relatively small storage capacity
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US Patent 7155597 Data processing device with aliased data pointer register
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US Patent 7159078 Computer system embedding sequential buffers therein for performing a digital signal processing data access operation and a method thereof
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US Patent 7159081 Automatic scenario management for a policy-based storage system
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US Patent 7159093 Development of a detailed logical volume configuration from high-level user requirements
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US Patent 7162585 Semiconductor memory device storing part of program designated by programmer, and software development apparatus for system using the same
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US Patent 7162587 Method and apparatus for recovering redundant cache data of a failed controller and reestablishing redundancy
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US Patent 7162588 Processor prefetch to match memory bus protocol characteristics
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US Patent 7162589 Methods and apparatus for canceling a memory data fetch
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US Patent 7162597 Backup technique for recording devices employing different storage forms
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US Patent 7162599 System and method for backing up and restoring data
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US Patent 7165137 System and method for booting from a non-volatile application and file storage device
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US Patent 7165146 Multiprocessing computer system employing capacity prefetching
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US Patent 7165153 Memory channel with unidirectional links
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US Patent 7165155 System and method for tracking changes associated with incremental copying
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US Patent 7167943 Memory apparatus
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US Patent 7167950 Storage system
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US Patent 7167959 Reordering hardware for mass storage command queue
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US Patent 7171511 WORM proving storage system
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US Patent 7171515 Storage unit with improved performance by purging unnecessary data and transferring data with high probability of future hits to a segment buffer
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US Patent 7171529 Single-chip microcomputer with read clock generating circuits disposed in close proximity to memory macros
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US Patent 7174415 Specialized memory device
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US Patent 7174437 Memory access management in a shared memory multi-processor system
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US Patent 7177980 Cache storage system and method
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US Patent 7177992 System for coupling data stored in buffer memories to backup storage devices
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US Patent 7177999 Reading extended data burst from memory
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US Patent 7181566 Scratch control memory array in a flash memory device
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US Patent 7181572 Cache updating method and apparatus
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US Patent 7181593 Active memory command engine and method
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US Patent 7185151 Data processing device characterized in its data transfer method, program for executing on a computer to perform functions of the device, and computer readable recording medium storing such a program
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US Patent 7185159 Technique for accessing memory in a data processing apparatus
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US Patent 7188226 Defective data site information storage
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US Patent 7188231 Multimedia address generator
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US Patent 7194590 Three data center adaptive remote copy
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US Patent 7197597 Performing lookup operations in a content addressable memory based on hashed values of particular use in maintaining statistics for packet flows
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US Patent 7216202 Method and apparatus for supporting one or more servers on a single semiconductor chip
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US Patent 7225304 Controller and method for writing data
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US Patent 7225315 High read performance file system and program
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US Patent 7231501 Method for avoiding aliased tokens during abnormal communications
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US Patent 7249206 Dynamic memory allocation between inbound and outbound buffers in a protocol handler
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US Patent 7254676 Processor cache memory as RAM for execution of boot code
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US Patent 7266675 Processor including a register file and method for computing flush masks in a multi-threaded processing system
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US Patent 7272677 Multi-channel synchronization for programmable logic device serial interface
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US Patent 7275138 System and method for controlling the updating of storage device
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US Patent 7277982 DRAM access command queuing structure
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US Patent 7281100 Data processing system and method
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US Patent 7281115 Method, system and program product for clearing selected storage translation buffer entries
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US Patent 7284100 Invalidating storage, clearing buffer entries, and an instruction therefor
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US Patent 7305538 Transparent local and distributed memory management system
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US Patent 7308528 Virtual tape library device
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US Patent 7340580 Storage device and information processing system
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US Patent 7353324 Semiconductor storage device and method of controlling the same
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US Patent 7475199 Scalable network file system
Edits on 1 Dec, 2021
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edited on 1 Dec, 2021
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US Patent 7475199 Scalable network file system
Edits on 25 Nov, 2021
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Golden AI
edited on 25 Nov, 2021
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US Patent 7353324 Semiconductor storage device and method of controlling the same
Edits on 23 Nov, 2021
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Golden AI
edited on 23 Nov, 2021
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Patent primary examiner of
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US Patent 7340580 Storage device and information processing system
Edits on 23 Nov, 2021
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Golden AI
edited on 23 Nov, 2021
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Patent primary examiner of
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US Patent 7308528 Virtual tape library device
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Golden AI
edited on 23 Nov, 2021
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Patent primary examiner of
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US Patent 7305538 Transparent local and distributed memory management system
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Golden AI
edited on 23 Nov, 2021
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Patent primary examiner of
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US Patent 7284100 Invalidating storage, clearing buffer entries, and an instruction therefor
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Golden AI
edited on 23 Nov, 2021
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Golden AI
edited on 23 Nov, 2021
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US Patent 7281100 Data processing system and method
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edited on 22 Nov, 2021
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US Patent 7277982 DRAM access command queuing structure
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Golden AI
edited on 22 Nov, 2021
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Patent primary examiner of
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US Patent 7275138 System and method for controlling the updating of storage device
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Golden AI
edited on 22 Nov, 2021
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US Patent 7272677 Multi-channel synchronization for programmable logic device serial interface
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Golden AI
edited on 22 Nov, 2021
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Golden AI
edited on 22 Nov, 2021
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Patent primary examiner of
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US Patent 7254676 Processor cache memory as RAM for execution of boot code
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Golden AI
edited on 22 Nov, 2021
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Patent primary examiner of
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US Patent 7249206 Dynamic memory allocation between inbound and outbound buffers in a protocol handler
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Golden AI
edited on 22 Nov, 2021
Edits made to:
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Patent primary examiner of
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US Patent 7231501 Method for avoiding aliased tokens during abnormal communications
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Golden AI
edited on 22 Nov, 2021
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Infobox
Patent primary examiner of
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US Patent 7225304 Controller and method for writing data
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Golden AI
edited on 22 Nov, 2021
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Infobox
Patent primary examiner of
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US Patent 7225315 High read performance file system and program
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Golden AI
edited on 22 Nov, 2021
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Infobox
Patent primary examiner of
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US Patent 7216202 Method and apparatus for supporting one or more servers on a single semiconductor chip
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Golden AI
edited on 22 Nov, 2021

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