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MAXENTRIC TECHNOLOGIES, LLC SBIR Phase II Award, March 2020

A SBIR Phase II contract was awarded to MaXentric Technologies in March, 2020 for $999,991.0 USD from the U.S. Department of Defense and Defense Microelectronics Activity.

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AbstractTimelineTable: Further ResourcesReferences
sbir.gov/node/1919387
Is a
SBIR/STTR Awards
SBIR/STTR Awards

SBIR/STTR Award attributes

SBIR/STTR Award Recipient
MaXentric Technologies
MaXentric Technologies
1
Government Agency
U.S. Department of Defense
U.S. Department of Defense
1
Government Branch
‌
Defense Microelectronics Activity
1
Award Type
SBIR1
Contract Number (US Government)
HQ072720C00041
Award Phase
Phase II1
Award Amount (USD)
999,9911
Date Awarded
March 17, 2020
1
End Date
March 31, 2022
1
Abstract

To meet the demands of the DMEA182-002 SBIR solicitation (“Front End of Line and Back End of Line Layer Fabrication Partitioning for the Purpose of Design Intellectual Property Protection”), the MaXentric and UCLA team proposes the HIGHFIVE (Heterogeneous Integration Guideline Highlighting Fabrication of Information Veiled Electronics), which provides a practical verification flow using the circuit-based model verification procedure. During Phase I, the team performed a trade-study on multiple chip-to-chip bonding process technologies. The team decided on one of candidates for UCLA’s Simple Universal Parallel intERface for CHIPS (SuperCHIPS) technology with the world finest pad pitch using the thermal compression bonding process. The team carefully selected figure-of-merit (FOM) circuits that were used to evaluate impact on the electrical performance when the manufacturing obfuscation technique is applied. During Phase I work, the UCLA and MaXentric characterized the chip-to-chip interconnect between the front-endof-line (active elements) and back-end-of-line (passive elements) layers, and simulate the performance of the FOM circuits for digital logic and analogy RF ASIC applications, respectively. During Phase II, the team will make a plan for fabrication and test of the FOM circuits, and develop a robust ecosystem for the interconnect.

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