SBIR/STTR Award attributes
Space travel and exploration, military applications, commercial aviation, unmanned vehicles and industrial/medical equipment are some examples of applications requiring electronics to withstand radiation and failures. NASA sub-topic S3.08 (Command, Data Handling, and Electronics) requires technology for fault-tolerant computing.nbsp; The topic further indicates that there is particular interest in a RISC-V based CPU intellectual property (IP) core designed to mitigate single event upsets (SEUs) to be delivered in either Verilog or VHDL language. RISC-V is an industry standard, open source architecture where the Government have full source code access and significant influence on its architecture and directions. This is very important for NASA and others to be able to fully validate the technology implemented for extremely high reliability, mission critical, and space exploration applications. Supporting system software would also be delivered andnbsp;as open source licensing. Topicnbsp;also requires mitigation method to reduce burden on code development time, hardware performance and size.nbsp; This work will provide the broadest family of 32/64-bit RISC-V configurable, fault tolerant CPU IP cores suitable for a wide range of applications from small nanosatellites to large vehicles. Along with the core libraries, an auto code generation tool, FPGA implementations and system software will be made available for fault tolerant applications development. This would be the first known US commercial effort and the most comprehensive solution for developing fault-tolerant RISC-V devices. This will also enable designers to quickly generate verified code and experiment with different configurations to make optimized trade-offs meeting specific application requirements for best power, size, cost. The development would be carried out by a team experienced in both fault-tolerant systems and embedded RISC CPU architecture with specific RISC-V SoC design experience
