SBIR/STTR Award attributes
LeWiz research from NASA Phase 1 I-Corps program showed verynbsp;strong interest in LeWiz solutions from NASA telescope team, DoD lab and commercial storage customers with potential for immediate revenue. Previously, LeWiz developed fault-tolerant (FT) 1) high performance network-on-chip bus (NOC) for multi-channel access supporting High Bandwidth Memory controller and/or high speed peripherals, and 2) 64-bit, 6-stage RISC-V CPU core with NOC interface capable up to 500K cores in a system. This Phase 2 proposed to further develop the Phase 1nbsp;solutions to meet the immediate customer requirements and productize the solutions for infusion intonbsp;NASA and commercial customer products. 2 subsystems would be developed i) spectrometer memory/peripheral subsystem with highly parallelized access channels supportingnbsp;DDR4 memory, 100Gbps Ethernet, multiple digital-to-analog converters, ii) RISC-V processor with enhanced NOC router integrated to the highly parallel NOC/HBM controller. The solution would also meet NASA SBIR Z2.02 Topic requirements for quot;A fault-tolerant RISC-V processor IP core ...nbsp;that is augmented to provide data parallelism, which is needed to accelerate image processing and science data processing.quot; andnbsp;enablingnbsp;future development of accelerators and co-processors for many-core high-performance processingnbsp;architecture advancing state of the art FT processors for space flights and autonomous applications. No other known solution is as advanced as the proposed for space applications. The project will be carried outnbsp;over 2 years in the US.
