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Kevin L. Ellis

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Ruslan Goriunov
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Patent primary examiner of
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US Patent 7089349 Internal maintenance schedule request for non-volatile memory system
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US Patent 7089369 Method for optimizing utilization of a double-data-rate-SDRAM memory system
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US Patent 7089387 Methods and apparatus for maintaining coherency in a multi-processor system
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US Patent 7089391 Managing a codec engine for memory compression/decompression operations using a data movement engine
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US Patent 7093093 Cache management system
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US Patent 7096322 Instruction processor write buffer emulation using embedded emulation control instructions
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US Patent 7096325 Method and apparatus for multistage volume locking
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US Patent 7107425 SDRAM controller that improves performance for imaging applications
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US Patent 7114049 Adaptive remote copy in a heterogeneous environment
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US Patent 7120749 Cache mechanism
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US Patent 7120760 Harvard architecture microprocessor having a linear addressable space
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US Patent 7124241 Apparatus and methodology for a write hub that supports high speed and low speed data rates
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US Patent 7124259 Methods and apparatus for indexed register access
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US Patent 7127566 Synchronizing memory copy operations with memory accesses
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US Patent 7127567 Performing memory RAS operations over a point-to-point interconnect
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US Patent 7136985 Method and system for fast data access using a memory array
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US Patent 7146462 Storage management method
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US Patent 7146464 Storage system
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US Patent 7149849 Caching based on access rights in connection with a content management server system or the like
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US Patent 7149851 Method and system for conservatively managing store capacity available to a processor issuing stores
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US Patent 7149871 Zone boundary adjustment for defects in non-volatile memories
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US Patent 7155577 Optimistic reads in a multi-node environment
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US Patent 7155592 System and method for onboard HDD defragmentation and combining multiple G-list entries
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US Patent 7162598 Storage system
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US Patent 7167948 Semiconductor memory device
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US Patent 7167949 Multi-processor type storage control apparatus for performing access control through selector
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US Patent 7167962 Remote copy for a storage controller with reduced data size
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US Patent 7167968 Storage pre-alignment and EBCDIC, ASCII and unicode basic latin conversions for packed decimal data
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US Patent 7171519 System, method and program for assessing the activity level of a database management system
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US Patent 7174423 Remote mirroring in a switched environment
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US Patent 7181565 Method and system for configuring parameters for flash memory
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US Patent 7185165 Invariant memory page pool and implementation thereof
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US Patent 7191283 Grouping of storage media based on parameters associated with the storage media
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US Patent 7194580 Disk array device, method of extending storage capacity and computer program
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US Patent 7197598 Apparatus and method for file level striping
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US Patent 7197609 Method and apparatus for multistage volume locking
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US Patent 7200729 Subsystem replacement method
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US Patent 7203731 Dynamic replication of files in a network storage system
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US Patent 7203800 Narrow/wide cache
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US Patent 7203815 Multi-level page cache for enhanced file system performance via read ahead
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US Patent 7206913 High speed memory system
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US Patent 7209982 Electronic apparatus including plural processors
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US Patent 7210009 Computer system employing a trusted execution environment including a memory controller configured to clear memory
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US Patent 7210015 Memory device having at least a first and a second operating mode
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US Patent 7213121 Memory device having asynchronous/synchronous operating modes
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US Patent 7219194 Method and circuit to implement digital delay lines
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US Patent 7219198 Facilitating communication within shared memory environments using lock-free queues
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US Patent 7225293 Method, system, and program for executing input/output requests
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US Patent 7228379 Systems and methods for removing data stored on long-term memory devices
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US Patent 7228392 Wireless data communications using FIFO for synchronization memory
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US Patent 7231498 Adaptive granularity refinement in detecting potential data races
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US Patent 7234021 Methods and apparatus for accessing data elements using improved hashing techniques
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US Patent 7234036 Method and apparatus for resolving physical blocks associated with a common logical block
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US Patent 7237061 Systems and methods for the efficient reading of data in a server system
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US Patent 7240147 Memory decoder and data bus for burst page read
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US Patent 7240153 Storage system and control method thereof for uniformly managing the operation authority of a disk array system
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US Patent 7240159 Data processor having cache memory
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US Patent 7240178 Non-volatile memory and non-volatile memory data rewriting method
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US Patent 7243201 Application-based commit for local storage subsystems and remote storage subsystems
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US Patent 7243207 Technique for translating a pure virtual file system data stream into a hybrid virtual volume
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US Patent 7243210 Extracted-index addressing of byte-addressable memories
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US Patent 7249215 System for configuring parameters for a flash memory
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US Patent 7249217 Content addressable memory (CAM) and method of downloading and banking filters
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US Patent 7249219 Method and apparatus to improve buffer cache hit rate
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US Patent 7254670 System, method, and apparatus for realizing quicker access of an element in a data structure
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US Patent 7254682 Selective file and folder snapshot image creation
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US Patent 7257682 Synchronizing memory copy operations with memory accesses
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US Patent 7257691 Writing and reading of data in probe-based data storage devices
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US Patent 7260686 System, apparatus and method for performing look-ahead lookup on predictive information in a cache memory
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US Patent 7266637 Storage management system
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US Patent 7266643 Information processing device
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US Patent 7266657 Data protection device and method of securing data
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US Patent 7266665 Method, system, and article of manufacture for remote copying of data
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US Patent 7272686 Storage system
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US Patent 7275133 Storage system
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US Patent 7275136 Virtualization system for computers with a region-based memory architecture
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US Patent 7277978 Runtime flash device detection and configuration for flash data management software
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US Patent 7280536 Fast path for performing data operations
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US Patent 7284089 Data storage device
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US Patent 7287132 Storage system, method of controlling storage system, and storage device
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US Patent 7290080 Application processors and memory architecture for wireless applications
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US Patent 7290091 Method and circuit to implement digital delay lines
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US Patent 7290110 System and method of squeezing memory slabs empty
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US Patent 7293073 Exactly once cache framework
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US Patent 7293140 Method for controlling storage policy according to volume activity
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US Patent 7296131 Management method and a management system for volume
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US Patent 7299323 Memory controller having a read-modify-write function
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US Patent 7299333 Computer system with storage system having re-configurable logical volumes
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US Patent 7299337 Enhanced shadow page table algorithms
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US Patent 7302530 Method of updating cache state information where stores only read the cache state information upon entering the queue
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US Patent 7302531 System and methods for sharing configuration information with multiple processes via shared memory
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US Patent 7302544 Method and apparatus for adaptive garbage collection
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US Patent 7302545 Method and system for fast data access using a memory array
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US Patent 7305535 Memory cards including a standard security function
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US Patent 7308541 Optimistic reads in a multi-node environment
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US Patent 7310704 System and method for performing online backup and restore of volume configuration information
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US Patent 7313650 Server and method for managing volume storing digital archive
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US Patent 7313654 Method for differential discarding of cached data in distributed storage systems
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US Patent 7313670 Data processing system and slave device
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US Patent 7315921 Apparatus and method for selective memory attribute control
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US Patent 7315929 Memory device
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US Patent 7318121 Synchronized mirrored data in a data storage device
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US Patent 7318129 Flash memory protection scheme for secured shared BIOS implementation in personal computers with an embedded controller
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US Patent 7320056 Multi-processor system
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US Patent 7328322 System and method for optimistic caching
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US Patent 7330933 Application cache pre-loading
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US Patent 7334087 Context-sensitive caching
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US Patent 7337272 Method and apparatus for caching variable length instructions
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US Patent 7337294 Method and apparatus for adjusting the performance of a synchronous memory system
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US Patent 7340494 Garbage-first garbage collection
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US Patent 7340579 Managing SANs with scalable hosts
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US Patent 7350027 Architectural support for thread level speculative execution
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US Patent 7350034 Architecture support of best-effort atomic transactions for multiprocessor systems
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US Patent 7350036 Technique to perform concurrent updates to a shared data structure
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US Patent 7353345 External observation and control of data in a computing processor
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US Patent 7353354 Application-based commit for local storage subsystems and remote storage subsystems
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US Patent 7353361 Page replacement policy for systems having multiple page sizes
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US Patent 7356654 Flexible multi-area memory and electronic device using the same
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US Patent 7356657 System and method for controlling storage devices
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US Patent 7356663 Layered memory architecture for deterministic finite automaton based string matching useful in network intrusion detection and prevention systems and apparatuses
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US Patent 7363464 Apparatus and method for reduction of processor power consumption
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US Patent 7366839 Storage system
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US Patent 7366861 Portable media synchronization manager
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US Patent 7370143 Controlling write request access to a non-volatile log
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US Patent 7370172 Method and system for strategy driven provisioning of storage in a storage area network
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US Patent 7380067 IO-stream adaptive write caching policy adjustment
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US Patent 7380070 Organization of dirty bits for a write-back cache
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US Patent 7380075 System and method for supporting variable-width memory accesses
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US Patent 7383317 Exactly once data framework system
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US Patent 7383381 Systems and methods for configuring a storage virtualization environment
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US Patent 7383385 Remote mirroring in a switched environment
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US Patent 7383412 On-demand memory synchronization for peripheral systems with multiple parallel processors
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US Patent 7386662 Coordination of caching and I/O management in a multi-layer virtualized storage environment
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US Patent 7389094 Wireless data communications using FIFO for synchronization memory
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US Patent 7392365 Dynamically changeable virtual mapping scheme
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US Patent 7395380 Selective snooping by snoop masters to locate updated data
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US Patent 7398347 Methods and apparatus for dynamic instruction controlled reconfigurable register file
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US Patent 7401179 Integrated circuit including a memory having low initial latency
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US Patent 7404035 System for controlling spinning of disk
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US Patent 7406558 Software method of emulation of EEPROM memory
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US Patent 7406572 Universal memory circuit architecture supporting multiple memory interface options
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US Patent 7409496 Storage management system, storage management server, and method and program for controlling data reallocation
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US Patent 7409502 Selective cache line allocation instruction execution and circuitry
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US Patent 7412564 Adaptive cache compression system
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US Patent 7421542 Technique for data cache synchronization
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US Patent 7428613 System and method for centralized partitioned library mapping
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US Patent 7447830 Information processing system and memory controller for controlling operation of memories
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US Patent 7447867 Non-intrusive address mapping having a modified address space identifier and circuitry therefor
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US Patent 7451269 Ordering real-time accesses to a storage medium
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US Patent 7451279 Storage system comprising a shared memory to access exclusively managed data
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US Patent 7451287 Storage system and remote copy method for storage system
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US Patent 7454574 Pre-fetch control method
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US Patent 7454583 Storage controller and control method for dynamically accomodating increases and decreases in difference data
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US Patent 7457914 Asynchronous event notification
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US Patent 7457919 Method for memory page management
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US Patent 7461198 System and method for configuration and management of flash memory
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US Patent 7461203 Disk array apparatus and method for controlling the same
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US Patent 7461211 System, apparatus and method for generating nonsequential predictions to access a memory
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US Patent 7461212 Non-inclusive cache system with simple control operation
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US Patent 7467256 Processor having content addressable memory for block-based queue structures
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US Patent 7467273 Storage apparatus for preventing falsification of data
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US Patent 7467282 Migrating a traditional volume to a virtual volume in a storage system
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US Patent 7469315 Storage controller, and method of controlling storage controller to improve the reliability of the storage controller
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US Patent 7469327 System and method for restricting access to logical volumes
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US Patent 7469330 Storage system having a first computer, a second computer connected to the first computer via a network, and a storage device system that is accessed by the second computer
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US Patent 7472225 Caching data
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US Patent 7472226 Methods involving memory caches
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US Patent 7475183 Large page optimizations in a virtual machine environment
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US Patent 7475202 Memory controller and method for optimized read/modify/write performance
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US Patent 7475213 Storage control system and storage control method
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US Patent 7475217 Method of managing storage capacity in storage system, a storage device and a computer system
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US Patent 7478207 Control system with a write filter for protection of data
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US Patent 7480779 Storage system, data restoring method, and data access method
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US Patent 7480783 Systems for loading unaligned words and methods of operating the same
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US Patent 7484041 Systems and methods for loading data into the cache of one processor to improve performance of another processor in a multiprocessor system
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US Patent 7484043 Multiprocessor system with dynamic cache coherency regions
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US Patent 7484047 Apparatus and method for composing a cache memory of a wireless terminal having a coprocessor
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US Patent 7484053 Cross-referencing cache line addresses with corresponding names
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US Patent 7484061 Method for performing swap operation and apparatus for implementing the same
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US Patent 7487298 Disk array device, method for controlling the disk array device and storage system
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US Patent 7487300 Data processing circuit with multiplexed memory
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US Patent 7487301 Method and system for accelerated access to a memory
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US Patent 7487323 Data storage system for storing data in different types of data storage media
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US Patent 7487324 Computer system
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US Patent 7487327 Processor and method for device-specific memory address translation
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US Patent 7493448 Prevention of conflicting cache hits without an attendant increase in hardware
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US Patent 7493462 Apparatus, system, and method for validating logical volume configuration
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US Patent 7493467 Address scrambling to simplify memory controller's address output multiplexer
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US Patent 7500054 Adaptive grouping in object RAID
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US Patent 7500061 Preload controller, preload control method for controlling preload of data by processor to temporary memory, and program
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US Patent 7500062 Fast path memory read request processing in a multi-level memory architecture
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US Patent 7500063 Method and apparatus for managing a cache memory in a mass-storage system
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US Patent 7500064 Data coherence system
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US Patent 7500071 Method for out of user space I/O with server authentication
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US Patent 7500081 Power-up implementation for block-alterable memory with zero-second erase time
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US Patent 7502904 Information processing system and management device for managing relocation of data based on a change in the characteristics of the data over time
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US Patent 7502908 Method for providing an address format compatible with different addressing formats used for addressing different sized address spaces
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US Patent 7506111 System and method for determining a number of overwitten blocks between data containers
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US Patent 7506115 Incremental provisioning of software
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US Patent 7506129 Memory leak detection
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US Patent 7509474 Robust index storage for non-volatile memory
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US Patent 7512733 Semiconductor memory and memory controller therefor
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US Patent 7512737 Size based eviction implementation
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US Patent 7512758 System and method for providing backup service continuity using a virtual backup service path
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US Patent 7512766 Controlling preemptive work balancing in data storage
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US Patent 7512767 Data compression method for supporting virtual memory management in a demand paging system
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US Patent 7512768 Dynamically sharing a stack between different code segments
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US Patent 7516274 Power conservation via DRAM access reduction
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US Patent 7516278 System controller, speculative fetching method, and information processing apparatus
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US Patent 7516279 Method using stream prefetching history to improve data prefetching performance.
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US Patent 7516286 Conversion between full-data and space-saving snapshots
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US Patent 7516295 Method of remapping flash memory
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US Patent 7519788 System and method for an asynchronous data buffer having buffer write and read pointers
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US Patent 7519792 Memory region access management
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US Patent 7523252 Data control apparatus functioning as a USB mass storage device
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US Patent 7523258 Disk array apparatus and method for controlling the same
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US Patent 7523262 Apparatus and method for providing global session persistence
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US Patent 7523275 Method, system, and program for maintaining a copy relationship between primary volumes and corresponding secondary volumes
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US Patent 7523287 Storage system and method for restricting access to virtual memory area by management host, and program for executing the same
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US Patent 7523288 Dynamic fragment mapping
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US Patent 7523289 Random access storage system capable of performing storage operations intended for alternative storage devices
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US Patent 7526600 Data management device and method for flash memory
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US Patent 7526614 Method for tuning a cache
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US Patent 7533231 Method and circuit for increasing the memory access speed of an enhanced synchronous memory
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US Patent 7536510 Hierarchical MRU policy for data cache
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US Patent 7536517 Direct-update software transactional memory
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US Patent 7536523 Point in time remote copy for multiple sites
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US Patent 7539813 Methods and apparatus for segregating a content addressable computer system
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US Patent 7539815 Method, system and circuit for managing task queues in a disk device controller
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US Patent 7539819 Cache operations with hierarchy control
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US Patent 7539821 First in first out eviction implementation
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US Patent 7543107 Method and apparatus for updating data on disk storage medium
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US Patent 7543109 System and method for caching data in a blade server complex
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US Patent 7543111 Method and device for storing content on a removable medium
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US Patent 7543113 Cache memory system and method capable of adaptively accommodating various memory line sizes
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US Patent 7543116 Data processing system, cache system and method for handling a flush operation in a data processing system having multiple coherency domains
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US Patent 7543122 System and method for obscuring hand-held device data traffic information
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US Patent 7546417 Method and system for reducing cache tag bits
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US Patent 7546419 Efficient data cache
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US Patent 7546428 Computer architecture for managing replication of data in a data storage environment
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US Patent 7546436 Storage device with SCSI formatting
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US Patent 7549011 Bit inversion in memory devices
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US Patent 7549020 Method and apparatus for raid on memory
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US Patent 7549022 Avoiding cache line sharing in virtual machines
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US Patent 7549024 Multi-processing system with coherent and non-coherent modes
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US Patent 7549027 System and method for managing replication of data in a data storage environment
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US Patent 7549038 Method and system for determining memory chunk location using chunk header information
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US Patent 7552273 Memory circuit and method for writing into a target memory area
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US Patent 7552276 System, method and program for managing storage
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US Patent 7552284 Least frequently used eviction implementation
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US Patent 7552303 Memory pacing
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US Patent 7552304 Cost-aware design-time/run-time memory management methods and apparatus
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US Patent 7552305 Dynamic and real-time management of memory
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US Patent 7555605 Data processing system having cache memory debugging support and method therefor
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US Patent 7558916 Storage system, data processing method and storage apparatus
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US Patent 7558925 Selective replication of data structures
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US Patent 7558937 Disk array device memory having areas dynamically adjustable in size
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US Patent 7562179 Maintaining processor resources during architectural events
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US Patent 7562180 Method and device for reduced read latency of non-volatile memory
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US Patent 7562197 Method and apparatus for multistage volume locking
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US Patent 7562201 Recording device and recording and reproducing device
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US Patent 7565476 Memory device
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US Patent 7565487 Computer system for managing data among virtual storage systems
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US Patent 7565489 Identifying relevant data to cache
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US Patent 7565501 Storage controller and data management method
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US Patent 7568068 Disk drive with cache having volatile and nonvolatile memory
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US Patent 7568070 Instruction cache having fixed number of variable length instructions
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US Patent 7568077 Information processing apparatus and file controller
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US Patent 7568080 Snapshot storage and management system with indexing and user interface
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US Patent 7571275 Flash real-time operating system for small embedded applications
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US Patent 7571276 Read operation for semiconductor memory devices
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US Patent 7571286 Reduced memory traffic via detection and tracking of temporally silent stores
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US Patent 7571290 Replica synchronization using copy-on-read technique
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US Patent 7571299 Methods and arrangements for inserting values in hash tables
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US Patent 7574553 Digital component power savings in a host device and method
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US Patent 7574557 Updated data write method using journal log
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US Patent 7577785 Content addressable memory with mixed serial and parallel search
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US Patent 7577797 Data processing system, cache system and method for precisely forming an invalid coherency state based upon a combined response
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US Patent 7577800 Method for borrowing and returning physical volumes
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US Patent 7577811 Memory controller for daisy chained self timed memory chips
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US Patent 7581065 Low locality-of-reference support in a multi-level cache hierachy
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US Patent 7584327 Method and system for proximity caching in a multiple-core system
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US Patent 7584328 Method, apparatus, and a system for efficient context switch
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US Patent 7584335 Methods and arrangements for hybrid data storage
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US Patent 7587548 Disk array apparatus and method for controlling the same
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US Patent 7590795 Flash memory systems utilizing direct data file storage
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US Patent 7590813 Cache scanning system and method
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US Patent RE40921 Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
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US Patent 7594062 Method for changing data of a data block in a flash memory having a mapping area, a data area and an alternative area
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US Patent 7594065 Using a processor to program a semiconductor memory
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US Patent 7594078 D-cache miss prediction and scheduling
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US Patent 7594083 Storage system and storage control device
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US Patent 7594088 System and method for an asynchronous data buffer having buffer write and read pointers
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US Patent 7596654 Virtual machine spanning multiple computers
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US Patent 7603514 Method and apparatus for concurrent and independent data transfer on host controllers
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US Patent 7603603 Configurable memory architecture with built-in testing mechanism
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US Patent 7603604 Test apparatus and electronic device
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US Patent 7606979 Method and system for conservatively managing store capacity available to a processor issuing stores
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US Patent 7607055 Semiconductor memory device and method of testing the same
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US Patent 7607066 Auto suggestion of coding error correction
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US Patent 7610523 Method and template for physical-memory allocation for implementing an in-system memory test
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US Patent 7610524 Memory with test mode output
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US Patent 7610530 Test data generator, test system and method thereof
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US Patent 7610532 Serializer/de-serializer bus controller interface
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US Patent 7610535 Boundary scan connector test method capable of fully utilizing test I/O modules
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US Patent 7613960 Semiconductor device test apparatus and method
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US Patent 7613961 CPU register diagnostic testing
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US Patent 7613972 Semiconductor integrated circuit, and designing method and testing method thereof
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US Patent 7613973 Method for providing bitwise constraints for test generation
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US Patent 7613986 Information recording device and method, information reproducing device and method, recording medium, program, and disc recording medium
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US Patent 7620857 Controllable delay device
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US Patent 7620862 Method of and system for testing an integrated circuit
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US Patent 7620863 Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits
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US Patent 7624319 Performance monitoring system
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US Patent 7624323 Method and apparatus for testing an IC device based on relative timing of test signals
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US Patent 7627793 Method and apparatus for generating and detecting initialization patterns for high speed DRAM systems
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US Patent 7627795 Pipelined data processor with deterministic signature generation
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US Patent 7631229 Selective bit error detection at a bus device
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US Patent 7631234 Test apparatus and test method
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US Patent 7631237 Multi-test method for using compare MISR
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US Patent 7634696 System and method for testing memory
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US Patent 7639444 Real-time channel adaptation
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US Patent 7640469 Electronic element comprising an electronic circuit which is to be tested and test system arrangement which is used to test the electronic element
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US Patent 7644333 Restartable logic BIST controller
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US Patent 7649855 Alternative 1000BASE-T scrambler
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US Patent 7650542 Method and system of using a single EJTAG interface for multiple tap controllers
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US Patent 7650547 Apparatus for locating a defect in a scan chain while testing digital logic
‌
US Patent 7650549 Digital design component with scan clock generation
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US Patent 7650550 Over temperature detection apparatus and method thereof
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US Patent 7650554 Method and an integrated circuit for performing a test
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US Patent 7650555 Method and apparatus for characterizing components of a device under test using on-chip trace logic analyzer
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US Patent 7653855 Random number test circuit, random number generation circuit, semiconductor integrated circuit, IC card and information terminal device
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US Patent 7657801 Test apparatus, program, and test method
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US Patent 7657807 Integrated circuit with embedded test functionality
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US Patent 7661043 Test apparatus, and method of manufacturing semiconductor memory
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US Patent 7661045 Method and system for enterprise memory management of memory modules
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US Patent 7661050 Method and system for formal verification of partial good self test fencing structures
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US Patent 7661052 Using statistical signatures for testing high-speed circuits
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US Patent 7664999 Real time testing using on die termination (ODT) circuit
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US Patent 7665003 Method and device for testing memory
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US Patent 7669090 Apparatus and method for verifying custom IC
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US Patent 7669100 System and method for testing and providing an integrated circuit having multiple modules or submodules
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US Patent 7673111 Memory system with both single and consolidated commands
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US Patent 7673203 Interconnect delay fault test controller and test apparatus using the same
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US Patent 7685480 Content addressable memory having redundant row isolated noise circuit and method of use
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US Patent 7685483 Design features for testing integrated circuits
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US Patent 7685485 Functional failure analysis techniques for programmable integrated circuits
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US Patent 7685486 Testing of an embedded multiplexer having a plurality of inputs
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US Patent 7685487 Simultaneous core testing in multi-core integrated circuits
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US Patent 7685488 Circuit interconnect testing arrangement and approach therefor
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US Patent 7685578 Method and protocol tester for decoding data encoded in accordance with a protocol description
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US Patent 7689876 Real-time optimized testing of semiconductor device
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US Patent 7689877 Method and system using checksums to repair data
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US Patent 7694194 Semiconductor device
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US Patent 7694199 Three boundary scan cell switches controlling input to output buffer
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US Patent 7698607 Repairing microdisplay frame buffers
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US Patent 7698622 Information recording device and method, information reproducing device and method, recording medium, program, and disc recording medium
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US Patent 7702971 System and method for predictive failure detection
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US Patent 7702983 Scan compression architecture for a design for testability compiler used in system-on-chip software design tools
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US Patent 7711996 Test system and method
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US Patent 7711999 Diagnostics of cable and link performance for a high-speed communication system
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US Patent 7712001 Semiconductor integrated circuit and method of testing semiconductor integrated circuit
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US Patent 7712002 Test circuit for semiconductor integrated circuit
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US Patent 7712014 Synchronizing clock and aligning signals for testing electronic devices
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US Patent 7716544 Path data transmission unit
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US Patent 7721168 eFuse programming data alignment verification
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US Patent 7725789 Apparatus for efficiently loading scan and non-scan memory elements
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US Patent 7730375 Method and apparatus for controlling operating modes of an electronic device
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US Patent 7734976 Synchronizing control of test instruments
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US Patent 7739565 Detecting corruption of configuration data of a programmable logic device
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US Patent 7743288 Built-in at-speed bit error ratio tester
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US Patent 7743296 Logic analyzer systems and methods for programmable logic devices
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US Patent 7743297 Electronic circuit and integrated circuit including scan testing circuit, and power consumption reducing method used for integrated circuit
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US Patent 7743304 Test system and method for testing electronic devices using a pipelined testing architecture
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US Patent 7743305 Test apparatus, and electronic device
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US Patent 7747915 System and method for improving the yield of integrated circuits containing memory
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US Patent 7747916 JTAG interface
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US Patent 7747918 JTAG bus communication method and apparatus
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US Patent 7752510 Integrated device for simplified parallel testing, test board for testing a plurality of integrated devices, and test system and tester unit
‌
US Patent 7752512 Semiconductor integrated circuit
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US Patent 7752518 System and method for increasing the extent of built-in self-testing of memory and circuitry
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US Patent 7757138 Semiconductor integrated circuit, test data generating device, LSI test device, and computer product
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US Patent 7761748 Methods and apparatus for managing clock skew between clock domain boundaries
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US Patent 7761761 Semiconductor integrated circuit, test data generating device, LSI test device, and computer product
‌
US Patent 7761763 System-on-chip (SOC) having built-in-self-test circuits and a self-test method of the SOC
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US Patent 7765080 System for testing smart cards and method for same
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US Patent 7765450 Methods for distribution of test generation programs
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US Patent 7770077 Using cache that is embedded in a memory hub to replace failed memory cells in a memory subsystem
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US Patent 7770082 Semiconductor integrated circuit and test method therefor
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US Patent 7770085 Replacement messages for identifying and preventing errors during the transmission of real time-critical data
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US Patent 7774664 Separate scan cell in series with TAP instruction register
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US Patent 7779314 System and related method for chip I/O test
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US Patent 7783830 Solid state device pattern for non-solid state storage media
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US Patent 7783856 Method and apparatus for management between virtualized machines and virtualized storage systems
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US Patent 7788547 Systems and methods for generation of communication channel fault information
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US Patent 7788552 Method to improve isolation of an open net fault in an interposer mounted module
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US Patent 7788556 System and method for evaluating an erroneous state associated with a target circuit
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US Patent 7788557 Baseboard testing interface and testing method thereof
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US Patent 7788564 Adjustable test pattern results latency
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US Patent 7793178 Cell supporting scan-based tests and with reduced time delay in functional mode
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US Patent 7793179 Test clock control structures to generate configurable test clocks for scan-based testing of electronic circuits using programmable test clock controllers
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US Patent 7793187 Checking output from multiple execution units
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US Patent 7797598 Dynamic timer for testbench interface synchronization
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US Patent 7797599 Diagnostic information capture from logic devices with built-in self test
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US Patent 7797603 Low power decompression of test cubes
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US Patent 7800412 Fault detection and isolation of redundant signals
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US Patent 7802157 Test mode for multi-chip integrated circuit packages
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US Patent 7805646 LSI internal signal observing circuit
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US Patent 7809908 Disk snapshot acquisition method
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US Patent 7809997 Semiconductor device, unique ID of semiconductor device and method for verifying unique ID
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US Patent 7810000 Circuit timing monitor having a selectable-path ring oscillator
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US Patent 7810003 Method of generating test clock signal and test clock signal generator for testing semiconductor devices
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US Patent 7814282 Memory share by a plurality of processors
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US Patent 7814289 Virtualization system and area allocation control method
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US Patent 7814290 Synchronous detection and signaling of memory quota violations for sequential memory allocation in a shared heap
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US Patent 7814377 Non-volatile memory system with self test capability
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US Patent 7814384 Electrical diagnostic circuit and method for the testing and/or the diagnostic analysis of an integrated circuit
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US Patent 7818491 Nonvolatile memory and electronic device for use therewith
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US Patent 7818520 Method of specifying access sequence of a storage device
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US Patent 7818642 Hierarchical test response compaction for a plurality of logic blocks
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US Patent 7818644 Multi-stage test response compactors
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US Patent 7822933 Enabling off-host data migration using volume translation mappings, snappoint maps and linked volume technologies
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US Patent 7823033 Data processing with configurable registers
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US Patent 7827365 Method and system to locate a storage device
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US Patent 7827458 Packet loss error recovery
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US Patent 7831762 Reducing the format time for bit alterable memories
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US Patent 7831765 Distributed programmable priority encoder capable of finding the longest match in a single operation
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US Patent 7831769 System and method for performing online backup and restore of volume configuration information
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US Patent 7836242 Method for page random write and read in blocks of flash memory
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US Patent 7836247 Method, apparatus, and computer program product for permitting access to a storage drive while the drive is being formatted
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US Patent 7836251 Storage controller, and method operative to relocate logical storage devices based on times and locations specified in a relocating plan
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US Patent 7836275 Method and apparatus for supporting address translation in a virtual machine environment
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US Patent 7840763 Methods and systems for achieving high assurance computing using low assurance operating systems and processes
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US Patent 7840770 Methods and systems for managing computer system configuration data
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US Patent 7840773 Providing memory management within a system management mode
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US Patent 7844506 Method, system, and program product for automatically populating a field of a record
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US Patent 7844783 Method for automatically detecting an attempted invalid access to a memory address by a software application in a mainframe computer
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US Patent 7844786 Addressing and command protocols for non-volatile memories utilized in recording usage counts
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US Patent 7849253 Method for fast access to flash-memory media
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US Patent 7849259 Disk controller response handler for write commands
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US Patent 7849282 Filesystem building method
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US Patent 7849284 Message memory for a communication protocol and method
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US Patent 7853716 Data storage system having packet switching network with latency arbitration
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US Patent 7853749 Flash drive fast wear leveling
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US Patent 7853762 Controlling access to non-volatile memory
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US Patent 7853771 Page allocation management for virtual memory
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US Patent 7856536 Providing a process exclusive access to a page including a memory address to which a lock is granted to the process
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US Patent 7856538 Methods, systems and computer readable medium for detecting memory overflow conditions
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US Patent 7861028 System and method for configuration and management of flash memory
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US Patent 7861041 Second chance replacement mechanism for a highly associative cache memory of a processor
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US Patent 7861042 Processor acquisition of ownership of access coordinator for shared resource
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US Patent 7861056 Methods, systems, and computer program products for providing memory management with constant defragmentation time
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US Patent 7865659 Removable storage device
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US Patent 7865660 Calibration of read/write memory access via advanced memory buffer
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US Patent 7865665 Storage system for checking data coincidence between a cache memory and a disk drive
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US Patent 7865666 Cache memory systems and methods thereof
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US Patent 7865679 Power interrupt recovery in a hybrid memory subsystem
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US Patent 7865683 Identifier associated with memory locations for managing memory accesses
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US Patent 7865685 Semiconductor memory asynchronous pipeline
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US Patent 7873784 Method and apparatus for evaluating and improving disk access time in a raid system
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US Patent 7873810 Microprocessor instruction using address index values to enable access of a virtual buffer in circular fashion
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US Patent 7877544 Storing redundant segments and parity information for segmented logical volumes
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US Patent 7877558 Memory controller prioritization scheme
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US Patent 7877560 Storage system with automated resource allocation
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US Patent 7877633 Highly reliable storage system and internal network thereof
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US Patent 7882314 Efficient scheduling of background scrub commands
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US Patent 7882323 Scheduling of background scrub commands to reduce high workload memory request latency
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US Patent 7882326 Live migration of a logical partition
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US Patent 7886114 Storage controller for cache slot management
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US Patent 7890713 Storage and data protection arrangements managing and setting an access attribute on a storage area basis
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US Patent 7890731 Clearing selected storage translation buffer entries based on table origin address
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US Patent 7890732 Memory card and semiconductor device
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US Patent 7895399 Computer system and control method for controlling processor execution of a prefetech command
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US Patent 7899975 Method for storing individual data items of a low-voltage switch
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US Patent 7899986 Method and system for controlling a hard disk drive using a multimediacard physical interface
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US Patent 7899996 Full track read for adaptive pre-fetching of data
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US Patent 7900001 System and method for obscuring hand-held device data traffic information
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US Patent 7904651 Storage device with disk power control based on logical storage area
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US Patent 7904658 Structure for power-efficient cache memory
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US Patent 7904660 Page descriptors for prefetching and memory management
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US Patent 7904694 Maintaining processor resources during architectural events
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US Patent 7908443 Memory controller and method for optimized read/modify/write performance
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US Patent 7913039 Array-type disk apparatus preventing data lost and providing improved failure tolerance
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US Patent 7913042 Virtual storage system control apparatus, virtual storage system control program and virtual storage system control method
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US Patent 7913048 Data subscribe-and-publish mechanisms and methods for producer-consumer pre-fetch communications
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US Patent 7913057 Translation lookaside buffer checkpoint system
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US Patent 7917687 Flash memory apparatus and access method to flash memory
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US Patent 7917706 SDRAM controller
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US Patent 7917710 Memory protection in a computer system employing memory virtualization
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US Patent 7917712 Method and system for governing access to storage device on SAN
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US Patent 7917715 Internet-safe computer
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US Patent 7925850 Page signature disambiguation for increasing the efficiency of virtual machine migration in shared-page virtualized computer systems
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US Patent 7929935 Wireless data communications using FIFO for synchronization memory
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US Patent 7930481 Controlling cached write operations to storage arrays
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US Patent 7930501 Memory card, access device, and processing method of memory card
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US Patent 7930511 Method and apparatus for management between virtualized machines and virtualized storage systems
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US Patent 7934048 Filtered register architecture to generate actuator signals
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US Patent 7934068 Storage system and method of taking over logical unit in storage system
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US Patent 7937540 Storage-access control system for preventing unauthorized access to a storage device
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US Patent 7937543 Determination of the frame age in a large real storage environment
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US Patent 7937550 Data recording device, data recording method, and recording medium
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US Patent 7941604 Distributed memory usage for a system having multiple integrated circuits each including processors
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US Patent 7941608 Cache eviction
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US Patent 7941609 HTTP acceleration by prediction and pre-fetching
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US Patent 7941628 Allocation of heterogeneous storage devices to spares and storage arrays
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US Patent 7945727 Disk drive refreshing zones in segments to sustain target throughput of host commands
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US Patent 7949847 Storage extent allocation method for thin provisioning storage
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US Patent 7953928 Apparatus and a method to make data sets conform to data management policies
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US Patent 7953929 Expanding the storage capacity of a virtualized data storage system
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US Patent 7953949 Data reallocation among storage systems
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US Patent 7953952 Computer and method for controlling whether or not to release all real storage areas assigned to virtual volume
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US Patent 7958306 Computer system and control method for the computer system
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US Patent 7962700 Systems and methods for reducing latency for accessing compressed memory using stratified compressed memory architectures and organization
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US Patent 7966469 Memory system and method for operating a memory system
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US Patent 7971000 Method and system for maintaining consistency of a cache memory accessible by multiple independent processes
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US Patent 7971001 Least recently used eviction implementation
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US Patent 7971002 Maintaining instruction coherency in a translation-based computer system architecture
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US Patent 7971003 Cache coherency in a shared-memory multiprocessor system
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US Patent 7971011 Remote copy method and storage system
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US Patent 7971023 Guaranteed memory card performance to end-of-life
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US Patent 7975100 Segmentation of logical volumes and movement of selected segments when a cache storage is unable to store all segments of a logical volume
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US Patent 7979624 Techniques to truncate data files in nonvolatile memory
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US Patent 7979636 Method of controlling semiconductor memory card system
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US Patent 7979641 Cache arrangement for improving raid I/O operations
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US Patent 7979643 Method for tuning a cache
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US Patent 7979650 Discovering data storage for backup
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US Patent 7984230 Allocation of logical volumes to flash memory drives
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US Patent 7984241 Controlling processor access to cache memory
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US Patent 7984256 Data processing system and method in which a participant initiating a read operation protects data integrity
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US Patent 7987324 Apparatus and method for verifying update data in mobile communication system
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US Patent 7987329 Storage system and method of controlling the same
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US Patent 7991950 Apparatus and method for incremental package deployment
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US Patent 7991966 Efficient usage of last level caches in a MCMP system using application level configuration
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US Patent 7996598 Memory management module
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US Patent 7996608 Providing redundancy in a storage system
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US Patent 7996620 High performance pseudo dynamic 36 bit compare
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US Patent 7996630 Method of managing memory in multiprocessor system on chip
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US Patent 8001317 Data writing method for non-volatile memory and controller using the same
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US Patent 8001343 Storage device with power control function
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US Patent RE42648 Semiconductor memory apparatus and method for writing data into the flash memory device
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US Patent 8006052 Systems and methods for tracking portions of a logical volume that have never been written by a host
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US Patent 8006063 Management method and a management system for volume
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US Patent 8010747 Method for tracking of non-resident pages
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US Patent 8010759 Extent redirect
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US Patent 8010763 Hypervisor-enforced isolation of entities within a single logical partition's virtual address space
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US Patent 7996608 Providing redundancy in a storage system
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