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Gopal C. Ray

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Edits on 14 Dec, 2021
"Remove inverse infobox"
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Golden AI
edited on 14 Dec, 2021
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Infobox (-115 properties)
Infobox
Patent primary examiner of
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US Patent 7093040 Secured inter-processor and virtual device communications system for use in a gaming system
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US Patent 7096295 Method and device for generating program interruptions in users of a bus system, and bus system
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US Patent 7096297 System and method for delaying an interrupt request until corresponding data is provided to a destination device
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US Patent 7096299 Method and apparatus for transferring system context information between mobile computer and base station
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US Patent 7099982 Multi-port communications integrated circuit
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US Patent 7103690 Communication between logical macros
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US Patent 7103691 Method, system and device for a processor to access devices of different speeds using a standard memory bus
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US Patent 7103693 Method for applying interrupt coalescing to incoming messages based on message length
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US Patent 7103694 Method and apparatus implementing a tuned stub SCSI topology
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US Patent 7107375 Method for improving selection performance by using an arbitration elimination scheme in a SCSI topology
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US Patent 7107382 Virtual peripheral component interconnect multiple-function device
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US Patent 7111096 Fast look-up of indirect branch destination in a dynamic translation system
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US Patent 7111106 Bus communication system by unrestrained connection and a communication control method therefor
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US Patent 7120721 Fibre channel architecture port having optical and copper connectors
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US Patent 7120723 System and method for memory hub-based expansion bus
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US Patent 7124233 USB composite device and method using hub link layer and UTMI interface
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US Patent 7127546 Simplified USB sharer having a busyness detection circuit
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US Patent 7130942 Interface bus protocol for managing transactions in a system of distributed microprocessor interfaces toward marco-cell based designs implemented as ASIC or FPGA bread boarding
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US Patent 7136957 Device bandwidth management using a bus configuration multiplexer
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US Patent 7136959 Data storage system having crossbar packet switching network
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US Patent 7139852 Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing
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US Patent 7139853 Data transmission/reception system, connection establishing method and information transmission/reception apparatus
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US Patent 7143216 System for configuring expandable buses in a multi-device storage container and related method
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US Patent 7143220 Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies
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US Patent 7143221 Method of arbitrating between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit of a data processing apparatus
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US Patent 7143226 Method and apparatus for multiplexing commands in a symmetric multiprocessing system interchip link
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US Patent 7146441 SRAM bus architecture and interconnect to an FPGA
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US Patent 7149834 Wireless device attachment and detachment system, apparatus and method
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US Patent 7149839 Wireless USB hardware scheduling
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US Patent 7155546 Multiple physical interfaces in a slot of a storage enclosure to support different storage interconnect architectures
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US Patent 7159046 Method and apparatus for configuring communication between devices in a computer system
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US Patent 7162558 Interrupt signal processing circuit for sending interrupt requests to a computer system
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US Patent 7165132 Processing node including a plurality of processor cores and an interconnect configurable in a test-mode to cause first and second transaction source indicators to be interchanged
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US Patent 7174403 Plural bus arbitrations per cycle via higher-frequency arbiter
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US Patent 7174409 System and method for memory hub-based expansion bus
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US Patent 7174413 Switching apparatus and method for providing shared I/O within a load-store fabric
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US Patent 7177965 Linking addressable shadow port and protocol for serial bus networks
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US Patent 7177967 Chipset support for managing hardware interrupts in a virtual machine system
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US Patent 7177969 Universal serial bus circuit which detects connection status to a USB host
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US Patent 7177973 Method and apparatus for extending communications over a universal serial bus through domain transformation
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US Patent 7185127 Method and an apparatus to efficiently handle read completions that satisfy a read request
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US Patent 7185128 System and method for machine specific register addressing in external devices
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US Patent 7185129 Method for configuring and/or operating an automation device having a master unit connected to one or more slave units
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US Patent 7188209 Apparatus and method for sharing I/O endpoints within a load store fabric by encapsulation of domain information in transaction layer packets
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US Patent 7191256 Combined host interface controller for conducting communication between a host system and multiple devices in multiple protocols
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US Patent 7191266 Method and apparatus for supporting and presenting multiple serial bus nodes using distinct configuration ROM images
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US Patent 7191268 Combined host interface controller for conducting communication between a host system and multiple devices in multiple protocols
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US Patent 7197588 Interrupt scheme for an Input/Output device
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US Patent 7197591 Dynamic lane, voltage and frequency adjustment for serial interconnect
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US Patent 7200700 Shared-IRQ user defined interrupt signal handling method and system
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US Patent 7200704 Virtualization of an I/O adapter port using enablement and activation functions
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US Patent 7203778 Method and system for notifying clients of a specific change in a data processing system
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US Patent 7206881 Arrangement and method for controlling dataflow on a data bus
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US Patent 7206887 System and method for memory hub-based expansion bus
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US Patent 7206889 Systems and methods for enabling communications among devices in a multi-cache line size environment and disabling communications among devices of incompatible cache line sizes
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US Patent 7209988 Management of the freezing of a functional module in a system on a chip
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US Patent 7209990 Maintain fairness of resource allocation in a multi-node environment
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US Patent 7209994 Processor that maintains virtual interrupt state and injects virtual interrupts into virtual machine guests
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US Patent 7213091 SRAM bus architecture and interconnect to an FPGA
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US Patent 7216189 Single BIOS technique for supporting processors with and without 64-bit extensions
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US Patent 7216191 System for programmed control of signal input and output to and from cable conductors
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US Patent 7216195 Architecture for managing disk drives
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US Patent 7219176 System and apparatus for early fixed latency subtractive decoding
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US Patent 7222210 System and method for memory hub-based expansion bus
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US Patent 7228366 Method and apparatus for deterministic removal and reclamation of work items from an expansion bus schedule
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US Patent 7228372 Data communication system with an SPI bus having a plurality of devices wherein data communications are enabled using communication protocols optimum to respective devices
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US Patent 7231474 Serial interface having a read temperature command
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US Patent 7231483 Bus station with integrated bus monitor function
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US Patent 7234018 Layered crossbar for interconnection of multiple processors and shared memories
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US Patent 7237049 Multimedia/secure digital cards and adapters for interfacing using voltage levels to determine host types and methods of operating
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US Patent 7240134 Circuit with processing prevention unit
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US Patent 7243175 I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures
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US Patent 7243180 Semiconductor memory device with bus driver circuit configured to transfer an output on a common bus onto an output bus with inversion or no inversion
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US Patent 7246185 Master and slave side arbitrators associated with programmable chip system components
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US Patent 7246186 Mobius time-triggered communication
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US Patent 7263565 Bus system and integrated circuit having an address monitor unit
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US Patent 7263569 Method and system for distributing power in a computer system
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US Patent 7263573 Wireless USB hardware scheduling
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US Patent 7266629 Data transfer control device and electronic instrument generating interface signal of signal type according to interface information set in internal register
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US Patent 7269682 Segmented interconnect for connecting multiple agents in a system
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US Patent 7272678 DSP bus monitoring apparatus and method
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US Patent 7272680 Method of transferring data between computer peripherals
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US Patent 7272681 System having parallel data processors which generate redundant effector date to detect errors
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US Patent 7281072 Redundant external storage virtualization computer system
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US Patent 7287114 Simulating multiple virtual channels in switched fabric networks
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US Patent 7290075 Performing arbitration in a data processing apparatus
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US Patent 7290076 Optmizing an interrupt-latency or a polling rate for a hardware platform and network profile combination by adjusting current timer values for both receive and transmit directions of traffic and calculating a new timer value to be used for both receive and transmit directions of traffic
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US Patent 7293127 Method and device for transmitting data using a PCI express port
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US Patent 7296103 Method and system for dynamically selecting wafer lots for metrology processing
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US Patent 7302511 Chipset support for managing hardware interrupts in a virtual machine system
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US Patent 7308521 Multi-port communications integrated circuit and method for facilitating communication between a central processing chipset and multiple communication ports
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US Patent 7310696 Method and system for coordinating interoperability between devices of varying capabilities in a network
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US Patent 7320046 Optical disc drive having a control board and driving unit in separate locations
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US Patent 7330920 Signal initiator and method for on-demand communication
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US Patent 7334071 Expansion of cross-domain addressing for PCI-express packets passing through non-transparent bridge
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US Patent 7337249 I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
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US Patent 7337258 Dynamically allocating devices to buses
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US Patent 7337261 Memory apparatus connectable to a host system having a USB connector
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US Patent 7343439 Removable modules with external I/O flexibility via an integral second-level removable slot
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US Patent 7350010 Method and an apparatus for switching root cells for a computer system without requiring the computer system to be re-booted
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US Patent 7350013 Bus communication apparatus for programmable logic devices and associated methods
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US Patent 7353307 Linking addressable shadow port and protocol for serial bus networks
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US Patent 7353316 System and method for re-routing signals between memory system components
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US Patent 7356630 Processor control device for stopping processor operation
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US Patent 7356638 Using out-of-band signaling to provide communication between storage controllers in a computer storage system
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US Patent 7370130 Core logic device of computer system
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US Patent 7370134 System and method for memory hub-based expansion bus
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US Patent 7373442 Method for using an expander to connect to different storage interconnect architectures
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US Patent 7373443 Multiple interfaces in a storage enclosure
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US Patent 7373447 Multi-port processor architecture with bidirectional interfaces between busses
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US Patent 7380037 Data transmitter between external device and working memory
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US Patent 7386645 System on a chip with an arbitration unit to grant right of access to a common resource in response to conflicting requests for access from initiator modules, and storage key incorporating the arbitration unit
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US Patent 7386647 System and method for processing an interrupt in a processor supporting multithread execution
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US Patent 7418527 Method and device for identifying devices connected to a communication network
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US Patent 7426593 Information processing system, reproducing terminal device and reproducing method, information processing device and method, and program for synchronous display of content
Edits on 1 Dec, 2021
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edited on 1 Dec, 2021
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Golden AI
edited on 1 Dec, 2021
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Infobox
Patent primary examiner of
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US Patent 7418527 Method and device for identifying devices connected to a communication network
Edits on 30 Nov, 2021
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edited on 30 Nov, 2021
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Golden AI
edited on 30 Nov, 2021
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Golden AI
edited on 30 Nov, 2021
Edits made to:
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Infobox
Patent primary examiner of
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US Patent 7380037 Data transmitter between external device and working memory
Edits on 26 Nov, 2021
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Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7373447 Multi-port processor architecture with bidirectional interfaces between busses
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Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7373443 Multiple interfaces in a storage enclosure
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Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7373442 Method for using an expander to connect to different storage interconnect architectures
Golden AI profile picture
Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7370134 System and method for memory hub-based expansion bus
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Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7370130 Core logic device of computer system
Edits on 25 Nov, 2021
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Golden AI
edited on 25 Nov, 2021
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Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7356630 Processor control device for stopping processor operation
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Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7353316 System and method for re-routing signals between memory system components
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Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7353307 Linking addressable shadow port and protocol for serial bus networks
Edits on 24 Nov, 2021
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Golden AI
edited on 24 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7350013 Bus communication apparatus for programmable logic devices and associated methods
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Golden AI
edited on 24 Nov, 2021
Edits on 23 Nov, 2021
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Golden AI
edited on 23 Nov, 2021
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Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7337258 Dynamically allocating devices to buses
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Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7337261 Memory apparatus connectable to a host system having a USB connector

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