SBIR/STTR Award attributes
As computational density for high-performance computing and big-data services continues to scale, performance scalability of next generation computing systems is becoming increasingly constrained by limitations in memory access, power dissipation and chip packaging. The processor-memory communication bottleneck, a major challenge in current multicore processors due to limited pin-out and power budget, presents a detrimental scaling barrier to data-intensive computing. A consortium team of small businesses and leading researchers that includes experts from photonics processor-memory architecture, III/V photonic laser design/fabrication, silicon photonics design/fabrication, photonics packaging and assembly, and FPGA-based high performance memory controller IP development – to collaboratively develop a commercialization path for a Photonic Memory Controller Module (P-MCM). The proposed work for Phase II (still ongoing) is to create an optical CPU-memory link utilizing both robust MZI based athermal bidirectional links (at 30Gbs) and also microring based denser WDM structures. The Phase II, specially the MZI based approach, enabled us to demonstrate record breaking optical links and set the stage for the commercialization stage. The exceptional high power and high temperature operation of the lasers developed by Freedom Photonics and the low loss coupling work performed by PLCC has made the planning for Phase IIb more straightforward. In this effort, we are proposing the commercialization of high-capacity short-reach (
