ENGIN-IC, INC. SBIR Phase II Award, September 2018

ENGIN-ICs objective in Phase II is to complete the design and layout of a < 2-dB noise figure, > 20-dB gain, and > 25-dBm OIP3 dual Ka-/Q-band LNA, requiring < 0.5 W DC power, and handling RF power levels to 1 W (requiring a GaAs Schottky diode limiter for GaAs HEMT processes, which ENGIN-IC will design, fabricate, and test), using two short gate length HEMT processes which can be space qualified.ENGIN-IC will fabricate and characterize the dual-band LNAs.A second design pass is planned on one of the dual-band LNA processes, if needed, to fully comply with AFRL requirements.A surface mount hot via interconnect package for the dual-band LNA will be demonstrated.ENGIN-IC will deliver bare die and packaged die that meet AFRL requirements.A prime will test dual-band LNAs to compare MMIC RF performance against current space hardware, and recommend how to proceed into production and flight hardware in Phase 3.