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Don Le

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Edits on 14 Dec, 2021
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edited on 14 Dec, 2021
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Patent primary examiner of
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US Patent 7088133 Programmable logic device with high speed serial interface circuitry
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US Patent 7091742 Fast ring-out digital storage circuit
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US Patent 7091747 Circuit for translating voltage signal levels
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US Patent 7095248 Hardware and software programmable fuses for memory repair
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US Patent 7095250 Single wire bus communication system with method for handling simultaneous responses from multiple clients
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US Patent 7102380 High speed integrated circuit
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US Patent 7102390 Method and apparatus for signal reception using ground termination and/or non-ground termination
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US Patent 7106097 IC with dual input output memory buffer
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US Patent 7106103 Selectable integrated circuit interface
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US Patent 7106104 Integrated line driver
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US Patent 7109754 Synchronization of programmable multiplexers and demultiplexers
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US Patent 7109755 Power delivery noise cancellation mechanism
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US Patent 7109756 Synchronization of programmable multiplexers and demultiplexers
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US Patent 7112991 Extended custom instructions
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US Patent 7112993 Non-volatile memory configuration scheme for volatile-memory-based programmable circuits in an FPGA
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US Patent 7112995 Low voltage to high voltage level shifter and related methods
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US Patent 7112997 Apparatus and methods for multi-gate silicon-on-insulator transistors
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US Patent 7113000 Bus agent having multiple reference levels
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US Patent 7123046 Apparatus for adaptively adjusting a data receiver
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US Patent 7123047 Dynamic on-die termination management
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US Patent 7123050 Programmable array logic circuit employing non-volatile ferromagnetic memory cells
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US Patent 7126378 High speed signaling system with adaptive transmit pre-emphasis
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US Patent 7129737 Method for avoiding transients during switching processes in integrated circuits, and an integrated circuit
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US Patent 7129742 Majority logic circuit
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US Patent 7129744 Programmable interconnect structures
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US Patent 7129749 Programmable logic device having a configurable DRAM with transparent refresh
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US Patent 7129752 High-speed lever shifter with AC feed-forward
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US Patent 7132855 Level shift circuit for use in semiconductor device
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US Patent 7132906 Coupler having an uncoupled section
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US Patent 7138823 Apparatus and method for independent control of on-die termination for output buffers of a memory device
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US Patent 7138826 Self-rewinding circuit
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US Patent 7138833 Selector circuit
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US Patent 7138834 Symmetric differential logic circuits
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US Patent 7142016 Input buffer of differential amplification type in semiconductor device
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US Patent 7142020 Resonant logic and the implementation of low power digital integrated circuits
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US Patent 7145363 Level shifter
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US Patent 7145364 Self-bypassing voltage level translator circuit
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US Patent 7148724 Signal output circuit
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US Patent 7151392 Output driver circuit
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US Patent 7154294 Comparators capable of output offset calibration
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US Patent 7154295 Semiconductor memory device with on-die termination circuit
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US Patent 7157934 Programmable asynchronous pipeline arrays
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US Patent 7161376 Variable impedence output buffer
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US Patent 7161378 Semiconductor memory device with on die termination circuit
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US Patent RE39469 Semiconductor integrated circuit with mixed gate array and standard cell
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US Patent 7167016 Operation mode setting circuit
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US Patent 7167018 Circuits, architectures, systems and methods for overvoltage protection
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US Patent 7170318 Impedance controller and impedance control method
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US Patent 7173454 Display device driver circuit
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US Patent 7176716 Look-up table structure with embedded carry logic
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US Patent 7176721 Signal receiver with data precessing function
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US Patent 7176722 Low power high performance inverter circuit
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US Patent 7176723 Translator circuit and method therefor
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US Patent 7176724 High speed chip-to-chip communication links
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US Patent 7180331 Voltage tolerant structure for I/O cells
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US Patent 7183793 Systems and methods for reducing electromagnetic emissions from a controller area network transceiver
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US Patent 7183797 Next generation 8B10B architecture
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US Patent 7183798 Synchronous memory
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US Patent 7183799 Physically-enforced time-limited cores and method of operation
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US Patent 7183800 Apparatus and methods for programmable logic devices with improved performance characteristics
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US Patent 7187195 Parallel compression test circuit of memory device
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US Patent 7187198 Programmable logic device
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US Patent 7187199 Structures and methods for testing programmable logic devices having mixed-fabric architectures
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US Patent 7187205 Integrated circuit storage element having low power data retention and method therefor
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US Patent 7190187 Power gating structure having data retention and intermediate modes
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US Patent 7190189 Device and method for voltage regulator with stable and fast response and low standby current
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US Patent 7193429 Serial data communication system having plurality of data transmission paths
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US Patent 7193434 Semiconductor integrated circuit
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US Patent 7193439 Segmented configuration of programmable logic devices
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US Patent 7193443 Differential output buffer with super size
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US Patent 7196542 Techniques for providing increased flexibility to input/output banks with respect to supply voltages
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US Patent 7196544 Communication device for a logic circuit
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US Patent 7199607 Pin multiplexing
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US Patent 7199608 Programmable logic device and method of configuration
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US Patent 7199610 Integrated circuit interconnect structure having reduced coupling between interconnect lines
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US Patent 7199612 Method and circuit for reducing HCI stress
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US Patent 7199615 High speed signaling system with adaptive transmit pre-emphasis and reflection cancellation
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US Patent 7202697 Programmable logic block having improved performance when functioning in shift register mode
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US Patent 7202702 Output buffer slew rate control using clock signal
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US Patent 7205794 Microprocessor resistant to power analysis
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US Patent 7205796 AND circuit
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US Patent 7208972 Circuit for generating a tracking reference voltage
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US Patent 7208975 SERDES with programmable I/O architecture
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US Patent 7208976 Look-up table based logic macro-cells
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US Patent 7208979 Signal level conversion circuit
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US Patent 7212030 Field programmable gate array long line routing network
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US Patent 7212035 Logic line driver system for providing an optimal driver characteristic
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US Patent 7212036 Driving apparatus of H bridge circuit and protection method of the same
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US Patent 7212037 Multi-level shifter having small chip size and small current consumption
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US Patent 7215138 Programmable lookup table with dual input and output terminals in shift register mode
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US Patent 7215139 Upgradeable and reconfigurable programmable logic device
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US Patent 7215145 Comparator circuit and power supply circuit
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US Patent 7215146 High speed buffered level-up shifters
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US Patent 7215147 System and method for providing power managed CML transmitters for use with main and auxiliary power sources
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US Patent 7215148 Programmable current output buffer
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US Patent 7215149 Interface circuitry for electrical systems
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US Patent 7215152 High performance adaptive load output buffer with fast switching of capacitive loads
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US Patent 7218138 Efficient implementations of the threshold-2 function
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US Patent 7218140 Integrated circuit having fast interconnect paths between carry chain multiplexers and lookup tables
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US Patent 7218144 Single and composite binary and multi-valued logic functions from gates and inverters
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US Patent 7218146 Transmitter circuit, receiver circuit, interface circuit, and electronic instrument
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US Patent 7221183 Tie-high and tie-low circuit
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US Patent 7221185 Method and apparatus for memory block initialization
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US Patent 7221186 Efficient tile layout for a programmable logic device
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US Patent 7224183 Fast method for functional mapping to incomplete LUT pairs
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US Patent 7224186 Semiconductor circuit device
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US Patent 7227382 Transmit based equalization using a voltage mode driver
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US Patent 7227383 Low leakage and data retention circuitry
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US Patent 7227384 Scan friendly domino exit and domino entry sequential circuits
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US Patent 7230452 Driver circuit
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US Patent 7230453 Output buffer providing multiple voltages
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US Patent 7230454 Serial audio output driver circuits and methods
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US Patent 7230455 Logic circuits utilizing gated diode sensing
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US Patent 7233164 Offset cancellation in a multi-level signaling system
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US Patent 7233167 Block symmetrization in a field programmable gate array
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US Patent 7236003 H-bridge circuit with shoot through current prevention during power-up
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US Patent 7236012 Data output driver that controls slew rate of output signal according to bit organization
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US Patent 7236013 Configurable output buffer and method to provide differential drive
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US Patent 7239174 Programmable interconnect structures
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US Patent 7239175 Look-up table based logic macro-cells
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US Patent 7239180 Programmable pin impedance reduction on multistandard input/outputs
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US Patent 7242215 Nanoscale latches and impedance-encoded logic for use in nanoscale state machines, nanoscale pipelines, and in other nanoscale electronic circuits
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US Patent 7242220 Signal transmitting system and method and signal driving device thereof
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US Patent 7242221 Selectable inversion of differential input and/or output pins in programmable logic devices
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US Patent 7245144 Adjustable differential input and output drivers
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US Patent 7245145 Memory module and method having improved signal routing topology
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US Patent 7248070 Method and system for using boundary scan in a programmable logic device
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US Patent 7248076 Dual-voltage three-state buffer circuit with simplified tri-state level shifter
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US Patent 7248078 Semiconductor device
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US Patent 7248079 Differential buffer circuit with reduced output common mode variation
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US Patent 7250788 Shift register, gate driving circuit and display panel having the same, and method thereof
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US Patent 7253658 Integrated circuit providing direct access to multi-directional interconnect lines in a general interconnect structure
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US Patent 7253659 Field programmable structured arrays
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US Patent 7256608 Method and apparatus for reducing leakage in integrated circuits
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US Patent 7256610 Programmable system on a chip for temperature monitoring and control
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US Patent 7256620 Selector circuit and semiconductor device
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US Patent 7259588 Tri-state detection circuit for use in devices associated with an imaging system
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US Patent 7259593 Unit circuit, method of controlling unit circuit, electronic device, and electronic apparatus
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US Patent 7262629 Apparatus and method for protecting from illegal copy
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US Patent 7265576 Programmable lookup table with dual input and output terminals in RAM mode
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US Patent 7265585 Method to improve current and slew rate ratio of off-chip drivers
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US Patent 7265586 Programmable differential signaling system
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US Patent 7265588 Dynamic clock change circuit
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US Patent 7268578 Transmission circuit, data-transfer control device and electronic equipment
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US Patent 7268579 Semiconductor integrated circuit having on-chip termination
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US Patent 7268580 Configuration circuits for three dimensional programmable logic devices
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US Patent 7268582 DPRIO for embedded hard IP
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US Patent 7268583 Reconfigurable integrated circuit device for automatic construction of initialization circuit
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US Patent 7271620 Variable impedance output buffer
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US Patent 7274210 Semiconductor integrated circuit
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US Patent 7276934 Integrated circuit with programmable routing structure including diagonal interconnect lines
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US Patent 7279928 xB/yB coder programmed within an embedded array of a programmable logic device
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US Patent 7279929 Integrated circuit with programmable routing structure including straight and diagonal interconnect lines
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US Patent 7279933 Output driver circuit
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US Patent 7279948 Schmidt trigger circuit having sensitivity adjusting function and semiconductor device including the same
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US Patent 7282955 Semiconductor memory device with on-die termination circuit
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US Patent 7285979 Apparatus and method for independent control of on-die termination for output buffers of a memory device
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US Patent 7285981 Configuration circuit for programmable logic devices
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US Patent 7285982 Configuration circuits for programmable logic devices
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US Patent 7285983 Programmable array logic circuit employing non-volatile ferromagnetic memory cells
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US Patent 7285984 Look-up table structure with embedded carry logic
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US Patent 7288925 Band gap reference voltage circuit
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US Patent 7292068 Output driver for use in semiconductor device
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US Patent 7295032 High-speed signal transmission system
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US Patent 7295035 Programmable logic device with enhanced logic block architecture
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US Patent 7295036 Method and system for reducing static leakage current in programmable logic devices
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US Patent 7295039 Buffer circuit
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US Patent 7298170 Safety system based on reconfigurable array of logic gates
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US Patent 7298172 Transmitter circuit, receiver circuit, interface circuit, and electronic instrument
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US Patent 7298176 Dual-gate dynamic logic circuit with pre-charge keeper
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US Patent 7301364 Output buffer circuit and semiconductor device
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US Patent 7304495 Pseudodynamic off-chip driver calibration
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US Patent 7304507 Modular buffering circuitry for multi-channel transceiver clock and other signals
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US Patent 7307445 Apparatus and methods for multi-gate silicon-on-insulator transistors
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US Patent 7307448 Interconnectable nanoscale computational stages
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US Patent 7307454 Apparatus and method for level shifting in power-on reset circuitry in dual power supply domains
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US Patent 7310007 Logic circuit, system for reducing a clock skew, and method for reducing a clock skew
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US Patent 7312628 Method and apparatus for CAN bus auto-termination
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US Patent 7312632 Fracturable lookup table and logic element
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US Patent 7317328 Test device for on die termination
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US Patent 7317336 Impedance matching circuit, input-output circuit and semiconductor test apparatus
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US Patent 7317337 Output driver in semiconductor device
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US Patent 7317339 N-domino register with accelerated non-discharge path
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US Patent 7321236 Apparatus and methods for programmable logic devices with improved performance characteristics
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US Patent 7321241 Bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control
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US Patent 7321243 P-domino register with accelerated non-charge path
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US Patent 7323905 Programmable structured arrays
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US Patent 7323907 Pre-emphasis driver control
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US Patent 7327159 Interface block architectures
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US Patent 7327160 SERDES with programmable I/O architecture
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US Patent 7327814 Amplitude and bandwidth pre-emphasis of a data signal
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US Patent 7330049 Adjustable transistor body bias generation circuitry with latch-up prevention
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US Patent 7330051 Innovated technique to reduce memory interface write mode SSN in FPGA
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US Patent 7332934 Programmable interconnect structures
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US Patent 7332935 Driver with variable output voltage and current
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US Patent 7332936 Semiconductor circuit, display device, electronic apparatus
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US Patent 7332938 Domino logic testing systems and methods
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US Patent 7336097 Look-up table structure with embedded carry logic
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US Patent 7336101 Control circuit and method
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US Patent 7345505 Alterable application specific integrated circuit (ASIC)
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US Patent 7345509 Integrated circuit devices with power supply detection circuitry
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US Patent 7345557 Multi-section coupler assembly
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US Patent 7348795 Configurable logic component without a local configuration memory and with a parallel configuration bus
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US Patent 7348803 Bi-directional bus buffer
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US Patent 7348804 Low leakage and data retention circuitry
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US Patent 7352203 Method to reduce power in active shield circuits that use complementary traces
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US Patent 7352210 Device and method for voltage regulator with stable and fast response and low standby current
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US Patent 7355441 Programmable logic devices with distributed memory and non-volatile memory
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US Patent 7355444 Single and composite binary and multi-valued logic functions from gates and inverters
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US Patent 7355450 Differential input buffers for low power supply
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US Patent 7355451 Common-mode shifting circuit for CML buffers
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US Patent 7358758 Apparatus and method for enabling a multi-processor environment on a bus
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US Patent 7358761 Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes
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US Patent 7358762 Parallel interface for configuring programmable devices
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US Patent 7358763 Driving method of an electric circuit
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US Patent 7358772 Reduced power output buffer
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US Patent 7358773 Signal level conversion circuit
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US Patent 7362125 Digital routing switch matrix for digitized radio-frequency signals
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US Patent 7362126 Floating CMOS input circuit that does not draw DC current
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US Patent 7362132 Reconfigurable integrated circuit device to automatically configure an initialization circuit
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US Patent 7365532 Apparatus to receive signals from electromagnetic coupler
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US Patent 7365570 Pseudo-differential output driver with high immunity to noise and jitter
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US Patent 7366926 On-chip supply regulators
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US Patent 7372290 System and method for using dummy cycles to mask operations in a secure microcontroller
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US Patent 7372295 Techniques for calibrating on-chip termination impedances
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US Patent 7372296 Configurable logic device providing enhanced flexibility, scalability and providing area efficient implementation of arithmetic operation on n-bit variables
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US Patent 7372299 Differential clock tree in an integrated circuit
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US Patent 7372300 Shift register and image display apparatus containing the same
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US Patent 7373540 System-on-chip having adjustable voltage level and method for the same
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US Patent 7378868 Modular I/O bank architecture
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US Patent 7382154 Reconfigurable network on a chip
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US Patent 7394284 Reconfigurable sequencer structure
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US Patent 7394291 High voltage tolerant output buffer
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US Patent 7394293 Circuit and method for rapid power up of a differential output driver
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US Patent 7397278 Level shifting circuit and display element driving circuit using same
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US Patent 7982413 Electronic ballast with dimming control from power line sensing
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US Patent 7986108 LED driver and start-up feedback circuit therein
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US Patent 7999480 Control circuit and flash system using same
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US Patent 8005522 Handheld electronic device
Edits on 8 Dec, 2021
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edited on 8 Dec, 2021
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US Patent 8005522 Handheld electronic device
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edited on 8 Dec, 2021
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Patent primary examiner of
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US Patent 7999480 Control circuit and flash system using same
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Golden AI
edited on 8 Dec, 2021
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Infobox
Patent primary examiner of
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US Patent 7986108 LED driver and start-up feedback circuit therein
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Golden AI
edited on 8 Dec, 2021
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Infobox (+1 properties)
Infobox
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US Patent 7982413 Electronic ballast with dimming control from power line sensing
Edits on 30 Nov, 2021
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Golden AI
edited on 30 Nov, 2021
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Infobox
Patent primary examiner of
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US Patent 7397278 Level shifting circuit and display element driving circuit using same
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Golden AI
edited on 30 Nov, 2021
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Infobox
Patent primary examiner of
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US Patent 7394293 Circuit and method for rapid power up of a differential output driver
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edited on 30 Nov, 2021
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Infobox
Patent primary examiner of
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US Patent 7394291 High voltage tolerant output buffer
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edited on 30 Nov, 2021
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Infobox
Patent primary examiner of
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US Patent 7394284 Reconfigurable sequencer structure
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Golden AI
edited on 30 Nov, 2021
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Infobox
Patent primary examiner of
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US Patent 7382154 Reconfigurable network on a chip
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edited on 29 Nov, 2021
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US Patent 7378868 Modular I/O bank architecture
Edits on 26 Nov, 2021
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Golden AI
edited on 26 Nov, 2021
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Patent primary examiner of
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US Patent 7373540 System-on-chip having adjustable voltage level and method for the same
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edited on 26 Nov, 2021
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Infobox
Patent primary examiner of
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US Patent 7372299 Differential clock tree in an integrated circuit
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Golden AI
edited on 26 Nov, 2021
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Infobox
Patent primary examiner of
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US Patent 7372300 Shift register and image display apparatus containing the same
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edited on 26 Nov, 2021
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Golden AI
edited on 26 Nov, 2021
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Patent primary examiner of
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US Patent 7372295 Techniques for calibrating on-chip termination impedances
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Golden AI
edited on 26 Nov, 2021
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Patent primary examiner of
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US Patent 7372290 System and method for using dummy cycles to mask operations in a secure microcontroller
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edited on 26 Nov, 2021
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Patent primary examiner of
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US Patent 7366926 On-chip supply regulators
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edited on 26 Nov, 2021
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Patent primary examiner of
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US Patent 7365570 Pseudo-differential output driver with high immunity to noise and jitter
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Golden AI
edited on 26 Nov, 2021
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Patent primary examiner of
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US Patent 7365532 Apparatus to receive signals from electromagnetic coupler

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