David J. Huisman

US Patent 11175921 Cognitive binary coded decimal to binary number conversion hardware for evaluating a preferred instruction variant based on feedback

US Patent 7356673 System and method including distributed instruction buffers for storing frequently executed instructions in predecoded form

US Patent 7356674 Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine

US Patent 7360028 Explicit store-to-instruction-space instruction for self-modifying code and ensuring memory coherence between instruction cache and shared memory using a no-snoop protocol

US Patent 7360059 Variable width alignment engine for aligning instructions based on transition between buffers

US Patent 7360063 Method for SIMD-oriented management of register maps for map-based indirect register-file access

US Patent 7363467 Dependence-chain processing using trace descriptors having dependency descriptors

US Patent 7363472 Memory access consolidation for SIMD processing elements having access indicators

US Patent 7363476 Method and apparatus to support an expanded register set

US Patent 7404069 Branch tracing generator device and method for a microprocessor supporting predicated instructions and expanded instructions

US Patent 7426628 Run-time node prefetch prediction in dataflow graphs

US Patent 7430653 Pipelined processor with multi-cycle grouping for instruction dispatch with inter-group and intra-group dependency checking

US Patent 7434032 Tracking register usage during multithreaded processing using a scoreboard having separate memory regions and storing sequential register size indicators

US Patent 7441102 Integrated circuit with functional state configurable memory and method of configuring functional states of the integrated circuit memory

US Patent 7447877 Method and apparatus for converting memory instructions to prefetch operations during a thread switch window

US Patent 7447879 Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache miss

US Patent 7447884 Multi-table branch prediction circuit for predicting a branch's target address based on the branch's delay slot instruction address

US Patent 7461235 Energy-efficient parallel data path architecture for selectively powering processing units and register files based on instruction type

US Patent 7464255 Using a shuffle unit to implement shift operations in a processor

US Patent 7478228 Apparatus for generating return address predictions for implicit and explicit subroutine calls

US Patent 7484075 Method and apparatus for providing fast remote register access in a clustered VLIW processor using partitioned register files

US Patent 7484079 Pipeline stage initialization via task frame accessed by a memory pointer propagated among the pipeline stages

US Patent 7487341 Handling address translations and exceptions of a heterogeneous resource of a processor using another processor resource

US Patent 7493476 Method and system for obtaining an immediate operand of a bytecode for use by a micro-sequence

US Patent 7493477 Method and apparatus for disabling a processor core based on a number of executions of an application exceeding a threshold

US Patent 7496737 High priority guard transfer for execution control of dependent guarded instructions

US Patent 7502917 High speed memory cloning facility via a lockless multiprocessor mechanism

US Patent 7512773 Context switching using halt sequencing protocol

US Patent 7516306 Computer program instruction architecture, system and process using partial ordering for adaptive response to memory latencies

US Patent 11188253 Using a data mover and a zero blocklist primitive to zero files on a virtual file system

US Patent 11188254 Using a data mover and a clone blocklist primitive to clone files on a virtual file system

US Patent 7526634 Counter-based delay of dependent thread group execution

US Patent 7536532 Merge operations of data arrays based on SIMD instructions

US Patent 7562206 Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions

US Patent 7565511 Working register file entries with instruction based lifetime

US Patent 7574584 Splitting execution of a floating-point add instruction between an integer pipeline for performing mantissa addition and a hardware state machine

US Patent 7577825 Method for data validity tracking to determine fast or slow mode processing at a reservation station

US Patent 7584344 Instruction for conditionally yielding to a ready thread based on priority criteria

US Patent 7587579 Processor core interface for providing external hardware modules with access to registers of the core and methods thereof

US Patent 7587583 Method and system for processing a “WIDE” opcode when it is not used as a prefix for an immediately following opcode

US Patent 7590825 Counter-based memory disambiguation techniques for selectively predicting load/store conflicts

US Patent 7596678 Method of shifting data along diagonals in a group of processing elements to transpose the data

US Patent 7600097 Detecting raw hazards in an object-addressed memory hierarchy by comparing an object identifier and offset for a load instruction to object identifiers and offsets in a store queue

US Patent 7627741 Instruction processing circuit including freezing circuits for freezing or passing instruction signals to sub-decoding circuits

US Patent 7631165 Processor organized in clusters of processing elements and cluster interconnections by a clustering process

US Patent 7631167 System for SIMD-oriented management of register maps for map-based indirect register-file access

US Patent 7631170 Program controlled embedded-DRAM-DSP having improved instruction set architecture

US Patent 7634637 Execution of parallel groups of threads with per-instruction serialization

US Patent 7647486 Method and system having instructions with different execution times in different modes, including a selected execution time different from default execution times in a first mode and a random execution time in a second mode

US Patent 7673123 System and method for classifying branch instructions into multiple classes for branch prediction

US Patent 7676652 Executing variable length instructions stored within a plurality of discrete memory address regions

US Patent 7676656 Minimizing unscheduled D-cache miss pipeline stalls in a cascaded delayed execution pipeline

US Patent 7681013 Method for variable length decoding using multiple configurable look-up tables

US Patent 7681014 Multithreading instruction scheduler employing thread group priorities

US Patent 7681016 Microprocessor instruction execution method for exploiting parallelism by time ordering operations in a single thread at compile time

US Patent 7681021 Dynamic branch prediction using a wake value to enable low power mode for a predicted number of instruction fetches between a branch and a subsequent branch

US Patent 7698537 Data processing apparatus for processing a stream of instructions in first and second processing blocks with the first processing block supporting register renaming and the second processing block not supporting register renaming

US Patent 7702885 Firmware extendable commands including a test mode command for a microcontroller-based flash memory controller

US Patent 7711927 System, method and software to preload instructions from an instruction set other than one currently executing

US Patent 7711937 Trap-based mechanism for tracking accesses of logical components

US Patent 7716457 Method and apparatus for counting instructions during speculative execution

US Patent 7721069 Low power, high performance, heterogeneous, scalable processor architecture

US Patent 7721071 System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor

US Patent 7721073 Conditional branch execution in a processor having a data mover engine that associates register addresses with memory addresses

US Patent 7721076 Tracking an oldest processor event using information stored in a register and queue entry

US Patent 7725688 System and method for storing states used to configure a processing pipeline in a graphics processing unit

US Patent 7734896 Enhanced processor element structure in a reconfigurable integrated circuit device

US Patent 7743238 Accessing items of architectural state from a register cache in a data processing apparatus when performing branch prediction operations for an indirect branch instruction

US Patent 7752423 Avoiding execution of instructions in a second processor by committing results obtained from speculative execution of the instructions in a first processor

US Patent 7769989 Processor for processing data using access addresses linked to the data type of the processed data

US Patent 7797515 System and method for limiting the number of unit processors for which suspension of processing is prohibited

US Patent 7809930 Selective suppression of register renaming

US Patent 7865704 Selective instruction breakpoint generation based on a count of instruction source events

US Patent 7904696 Communication paths for enabling inter-sequencer communication following lock competition and accelerator registration

US Patent 7904701 Activating a design test mode in a graphics card having multiple execution units to bypass a host cache and transfer test instructions directly to an instruction cache

US Patent 7925868 Suppressing register renaming for conditional instructions predicted as not executed

US Patent 7925869 Instruction-level multithreading according to a predetermined fixed schedule in an embedded processor using zero-time context switching

US Patent 7934075 Method and apparatus for monitoring inputs to an asyncrhonous, homogenous, reconfigurable computer array

US Patent 7937564 Emit vector optimization of a trace

US Patent 7937570 Termination of in-flight asynchronous memory move

US Patent 7941646 Completion continue on thread switch based on instruction progress metric mechanism for a microprocessor

US Patent 7953957 Mapping and distributing parallel algorithms to compute nodes in a parallel computer based on temperatures of the compute nodes in a hardware profile and a hardware independent application profile describing thermal characteristics of each parallel algorithm

US Patent 7962718 Methods for performing extended table lookups using SIMD vector permutation instructions that support out-of-range index values

US Patent 7971042 Microprocessor system and method for instruction-initiated recording and execution of instruction sequences in a dynamically decoupleable extended instruction pipeline

US Patent 7984269 Data processing apparatus and method for reducing issue circuitry responsibility by using a predetermined pipeline stage to schedule a next operation in a sequence of operations defined by a complex instruction

US Patent 7984273 System and method for using a mask register to track progress of gathering elements from memory

US Patent 7987341 Computing machine using software objects for transferring data that includes no destination information

US Patent 7996497 Method of handling duplicate or invalid node controller IDs in a distributed service processor environment

US Patent 7996656 Attaching and virtualizing reconfigurable logic units to a processor