DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) - a type of computer memory used in computing machinery as a RAM and video memory. Came to replace the SDR SDRAM type memory.
When using DDR SDRAM double speed is achieved than SDRAM, by reading commands and data not only on the front, as in SDRAM, but also on the fall of the clock signal. This doubles the data transfer rate without increasing the memory bus clock signal frequency. Thus, when running DDR at 100 MHz we get an effective frequency of 200 MHz (when compared with the SDR SDRAM counterpart). There is a note in JEDEC specification that it is incorrect to use the term "MHz" in DDR, it is correct to specify the speed of "millions of transfers per second through one data pin".
Specific mode of memory modules is dual-channel mode.
DDR SDRAM memory chips were produced in TSOP-packages and (mastered later) in BGA-packages (FBGA), manufactured according to the standards of 130- and 90-nanometer process:
- The supply voltage of the chips: 2.6 V ± 0.1 V.
- Power consumption: 527 mW.
- I/O interface: SSTL_2.
The memory bus width is 64 bits, i.e. 8 bytes are transmitted per clock cycle. This gives us the following formula for calculating the maximum transfer rate for a given memory type: (memory bus clock frequency) x 2 (data transfer twice per cycle) x 8 (number of bytes transferred per cycle). For example, a special "2n Prefetch" architecture is used to allow data to be transferred twice per clock cycle. The internal data bus is twice as wide as the external bus; when transmitting data, the first half of the data bus on the rising edge of the clock signal is transmitted first, and then the second half of the data bus on the falling edge.
In addition to the doubled data transfer, DDR SDRAM has several other fundamental differences from simple SDRAM memory. Mainly, they are technological ones. For example, was added signal QDS, which is located on the circuit board, along with data lines. This signal is used to synchronize the data transfer. If two memory modules are used, the data from them comes to the memory controller with a small difference due to the different distance. The problem arises in the choice of synchronous signal to read them, and using QDS successfully solves this. Roughly speaking, if there are 2 or more RAM slots on the motherboard, the near slot will wait for the far slot.
JEDEC sets standards for DDR SDRAM speeds, divided into two parts: the first for memory chips and the second for memory modules, which actually house the memory chips.
Each DDR SDRAM module includes several identical DDR SDRAM chips. For modules without error correction (ECC) their number is a multiple of 4, for modules with ECC - the formula is 4+1.
Memory Chips Specification
- DDR200: DDR SDRAM memory operating at 100MHz
- DDR266: DDR SDRAM memory operating at 133MHz
- DDR333: DDR SDRAM memory operating at 166MHz
- DDR400: DDR SDRAM memory operating at 200 MHz
- Chip capacity (DRAM density). It is expressed in megabits, for example, 256 Mbits is a 32 megabyte chip.
- DRAM organization. Written as 64M x 4, where 64M is the number of elementary storage cells (64 million) and x4 (pronounced "by four") is the bit depth of the chip, that is the bit depth of each cell. DDR chips are available in x4 and x8, the latter being cheaper in terms of capacity per megabyte but not allowing the Chipkill, Memory scrubbing and Intel Single-device data correction functions.
DDR SDRAM modules are in a DIMM form factor. Each module contains several identical memory chips and a configuration chip Serial presence detection[en]. Modules of registered memory also have register chips that buffer and amplify the signal on the bus, non-register (unbuffered) memory modules do not.
- Capacity. Specified in megabytes or gigabytes.
- The number of chips (# of DRAM Devices). A multiple of 8 for non-ECC modules, a multiple of 9 for modules with ECC. Chips may be located on one or both sides of the module. Maximum number of DIMMs that can be placed is 36 (9x4).
- Number of DRAM rows (ranks). Chips, as you can see from their specifications, have a 4 or 8-bit data bus. To provide a wider bandwidth (e.g., DIMM requires 64 bits and 72 bits for ECC memory), the chips are linked in ranks. A memory rank shares a common address bus and complementary data lines. Several ranks can be placed on a single module. But if more memory is needed, it is possible to add more ranks by installing several modules on one board and using the same principle: all ranks sit on one bus, only Chip select[en] is different - each one has its own. A large number of ranks electrically stresses the bus, or rather the controller and memory chips, and slows them down. Hence began to apply multichannel architecture, which also allows independent access to multiple modules.
- Delays (timings): CAS Latency (CL), Clock Cycle Time (tCK), Row Cycle Time (tRC), Refresh Row Cycle Time (tRFC), Row Active Time (tRAS).
The characteristics of the modules and the chips that make them up are related.
The volume of a module is equal to the product of the volume of one chip by the number of chips. If ECC is used, this number is further multiplied by a factor of 8/9, since each byte has one bit of redundancy for error control. So, the same memory module can be configured with a larger number (36) of small chips or with a smaller number (9) of larger chips.
The total capacity of a module is equal to the product of the capacity of one chip by the number of chips and is equal to the product of the number of ranks by 64 (72) bits. So, increasing the number of chips or using x8 chips instead of x4 leads to increasing the number of ranks of the module.