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Andrew Q. Tran

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Edits on 14 Dec, 2021
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Golden AI
edited on 14 Dec, 2021
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Patent primary examiner of
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US Patent 7088635 Bank based self refresh control apparatus in semiconductor memory device and its method
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US Patent 7092300 Memory apparatus having a short word line cycle time and method for operating a memory apparatus
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US Patent 7092311 Content addressable memory (CAM) devices that utilize priority class detectors to identify highest priority matches in multiple CAM arrays and methods of operating same
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US Patent 7095641 Content addressable memory (CAM) devices having priority class detectors therein that perform local encoding of match line signals
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US Patent 7095669 Refresh for dynamic cells with weak retention
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US Patent 7099180 Phase change memory bits reset through a series of pulses of increasing amplitude
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US Patent 7099231 Interleaving memory blocks to relieve timing bottleneck in a multi-queue first-in first-out memory system
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US Patent 7102927 Memory devices and programming methods that simultaneously store erase status indications for memory blocks
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US Patent 7102954 Semiconductor integrated circuit device having logic circuit and dynamic random access memory on the same chip
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US Patent 7106622 Phase-change memory device capable of preprogramming memory cells optically and reading/writing memory cells electrically
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US Patent 7106627 Nonvolatile semiconductor memory device with redundancy and security information circuitry
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US Patent 7113430 Device for reducing sub-threshold leakage current within a high voltage driver
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US Patent 7113438 Semiconductor memory device and connecting method of sense amplifier
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US Patent 7120053 Semiconductor intergrated circuit device with a main cell array and a fuse cell array whose word lines and bit lines are extended in the same directions
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US Patent 7120061 Method and apparatus for a dual power supply to embedded non-volatile memory
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US Patent 7123513 Erase verify for non-volatile memory using a reference current-to-voltage converter
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US Patent 7123516 Erase verify for nonvolatile memory using bitline/reference current-to-voltage converters
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US Patent 7133307 Resistive memory element sensing using averaging
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US Patent 7133312 Readout circuit for semiconductor memory device based on a number of pulses generated by a voltage-controlled oscillator
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US Patent 7133314 Non-volatile semiconductor memory device with reduced chip real estate area for transfer transistors
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US Patent 11177371 Transistor with superposed bars and double-gate structure
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US Patent 7139182 Cutting CAM peak power by clock regioning
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US Patent 7139208 Refresh-free dynamic semiconductor memory device
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US Patent 7145829 Single cycle refresh of multi-port dynamic random access memory (DRAM)
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US Patent 7154774 Detecting switching of access elements of phase change memory cells
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US Patent 7158407 Triple pulse method for MRAM toggle bit characterization
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US Patent 7164606 Reverse fowler-nordheim tunneling programming for non-volatile memory cell
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US Patent 7167390 Storage device with resistive memory cells enduring repetitive data writing
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US Patent 7167396 Erase verify for nonvolatile memory using reference current-to-voltage converters
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US Patent 7173874 Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface
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US Patent 7177187 Semiconductor device having a nonvolatile memory array and an authentication circuit arranged in a vertical stack configuration
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US Patent 7177215 Semiconductor memory device operating at high speed and low power consumption
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US Patent 7193892 Magnetic switching with expanded hard-axis magnetization volume at magnetoresistive bit ends
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US Patent 7193896 Multi-value semiconductor memory device and method capable of caching a lower page data upon an incomplete write of an upper page data
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US Patent 7196934 Non-volatile memory with erase verify circuit having comparators indicating under-erasure, erasure, and over-erasure of memory cells
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US Patent 7196955 Hardmasks for providing thermally assisted switching of magnetic memory elements
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US Patent 7200019 Dual match line architecture for content addressable memories and other data structures
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US Patent 7203082 Race condition improvements in dual match line architectures
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US Patent 7206249 SRAM cell power reduction circuit
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US Patent 7208323 Method for forming magneto-resistive memory cells with shape anisotropy
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US Patent 7209387 Non-volatile programmable fuse apparatus in a flash memory with pairs of supercells programmed in a complementary fashion
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US Patent 7215595 Memory device and method using a sense amplifier as a cache
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US Patent 7218554 Method of refreshing charge-trapping non-volatile memory using band-to-band tunneling hot hole (BTBTHH) injection
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US Patent 7221600 Arithmetic circuit integrated with a variable resistance memory element
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US Patent 7224613 Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states
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US Patent 7224634 Hardware security device for magnetic memory cells
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US Patent 7227796 Memory system mounted directly on board and associated method
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US Patent 7227802 Multi-time programmable semiconductor memory device and multi-time programming method therefor
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US Patent 7230847 Substrate electron injection techniques for programming non-volatile charge storage memory cells
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US Patent 7230855 Erase verify for non-volatile memory using bitline/reference current-to-voltage converters
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US Patent 7233525 Method of converting contents of flash memory cells in the presence of leakage
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US Patent 7236399 Method for erase-verifying a non-volatile memory capable of identifying over-erased and under-erased memory cells
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US Patent 7236400 Erase verify for non-volatile memory using a bitline current-to-voltage converter
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US Patent 7239553 Method and apparatus for reference cell adjusting in a storage device
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US Patent 7242608 Semiconductor memory device having a floating storage bulk region capable of holding/emitting excessive majority carriers
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US Patent 7251183 Static random access memory having a memory cell operating voltage larger than an operating voltage of a peripheral circuit
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US Patent 7254056 Apparatus for optically pre-programming electrically-programmable phase-change memory devices
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US Patent 7257015 Semiconductor memory device having a floating storage bulk region
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US Patent 7259983 Page buffer architecture for programming, erasing and reading nanoscale resistive memory devices
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US Patent 7260007 Temperature determination and communication for multiple devices of a memory module
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US Patent 7266017 Method for selective erasing and parallel programming/verifying of cell blocks in a flash EEprom system
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US Patent 7269070 Flash memory device with multiple erase voltage levels
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US Patent 7272028 MRAM cell with split conductive lines
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US Patent 7272041 Memory array with pseudo single bit memory cell and method
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US Patent 7274613 Dynamic random access memory (DRAM) capable of canceling out complementary noise development in plate electrodes of memory cell capacitors
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US Patent 7283381 System and methods for addressing a matrix incorporating virtual columns and addressing layers
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US Patent 7283397 Flash EEprom system capable of selective erasing and parallel programming/verifying memory cell blocks
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US Patent 7286386 Semiconductor device
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US Patent 7286389 Low-power, p-channel enhancement-type metal-oxide semiconductor field-effect transistor (PMOSFET) SRAM cells
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US Patent 7289377 Internal voltage generator capable of regulating an internal voltage of a semiconductor memory device
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US Patent 7292471 Semiconductor memory device having a voltage-controlled-oscillator-based readout circuit
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US Patent 7292483 Back-bias voltage generator for decreasing a current consumption of a self-refresh operation
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US Patent 7295456 Chain ferroelectric random access memory (CFRAM) having an intrinsic transistor connected in parallel with a ferroelectric capacitor
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US Patent 7295469 Nonvolatile semiconductor memory device with a ROM block settable in a write/erase inhibit mode
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US Patent 7298658 Semiconductor memory device using row redundancy and I/O redundancy scheme based on a preset order and a defect order
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US Patent 7301850 Content addressable memory (CAM) devices having bidirectional interface circuits therein that support passing word line and match signals on global word lines
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US Patent 7304879 Non-volatile memory element capable of storing irreversible complementary data
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US Patent 7304905 Throttling memory in response to an internal temperature of a memory device
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US Patent 7304910 Semiconductor memory device with sub-amplifiers having a variable current source
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US Patent 7307885 Multi-value nonvolatile semiconductor memory device equipped with reference cell and load balancing circuit
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US Patent 7307913 Clock control device for toggling an internal clock of a synchronous DRAM for reduced power consumption
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US Patent 7310262 Ferroelectric memory capable of continuously fast transferring data words in a pipeline
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US Patent 7310266 Semiconductor device having memory cells implemented with bipolar-transistor-antifuses operating in a first and second mode
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US Patent 7313016 Method of resetting phase change memory bits through a series of pulses of increasing amplitude
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US Patent 7315479 Redundant memory incorporating serially-connected relief information storage
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US Patent 7317633 Protection of NROM devices from charge damage
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US Patent 7317639 Two-bit charge trap nonvolatile memory device and methods of operating and fabricating the same
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US Patent 7317651 Anti-fuse circuit and anti-fusing method
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US Patent 7319612 Performing multiple read operations via a single read command
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US Patent 7327595 Dynamically read fuse cell
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US Patent 7327608 Program time adjustment as function of program voltage for improved programming speed in programming method
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US Patent 7327609 Methods of program-verifying a multi-bit nonvolatile memory device and circuit thereof
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US Patent 7330373 Program time adjustment as function of program voltage for improved programming speed in memory system
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US Patent 7330376 Method for memory data storage by partition into narrower threshold voltage distribution regions
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US Patent RE40075 Method of multi-level storage in DRAM and apparatus thereof
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US Patent 7333380 SRAM memory device with flash clear and corresponding flash clear method
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US Patent 7333386 Extraction of a binary code based on physical parameters of an integrated circuit through programming resistors
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US Patent 7336518 Layout for equalizer and data line sense amplifier employed in a high speed memory device
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US Patent 7336519 Stacked integrated circuit device/data processor device having a flash memory formed on top of a buffer memory
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US Patent 7336552 Sense amplifier connecting/disconnecting circuit arrangement and method for operating such a circuit arrangement
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US Patent 7355872 Segmented content addressable memory architecture for improved cycle time and reduced power consumption
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US Patent 7372717 Methods for resistive memory element sensing using averaging
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US Patent 7372730 Method of reading NAND memory to compensate for coupling between storage elements
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US Patent 7379354 Methods and apparatus to provide voltage control for SRAM write assist circuits
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US Patent 7382655 Access time adjusting circuit and method for non-volatile memory
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US Patent 7388775 Detecting switching of access elements of phase change memory cells
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US Patent 7391637 Semiconductor memory device with high permeability composite films to reduce noise in high speed interconnects
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US Patent 7391658 Internal voltage generator capable of regulating an internal voltage of a semiconductor memory device
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US Patent 7394680 Resistance change memory device having a variable resistance element with a recording layer electrode served as a cation source in a write or erase mode
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US Patent 7397717 Serial peripheral interface memory device with an accelerated parallel mode
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US Patent 7400522 Resistance change memory device having a variable resistance element formed of a first and second composite compound for storing a cation
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US Patent 7405978 Nonvolatile semiconductor memory device having bitlines extending from cell array in single direction
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US Patent 7408819 Semiconductor memory device with a page buffer having an improved layout arrangement
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US Patent 7411844 Semiconductor memory device having a redundancy information memory directly connected to a redundancy control circuit
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US Patent 7414897 Internal voltage generator capable of regulating an internal voltage of a semiconductor memory device
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US Patent 7417897 Method for reading a single-poly single-transistor non-volatile memory cell
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US Patent 7417918 Method and apparatus for configuring the operating speed of a programmable logic device through a self-timed reference circuit
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US Patent 7420839 Magnetization reversal method for applying a multi-directional external magnetic field to a perpendicular magnetoresistive film
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US Patent 7420841 Memory device and method for transforming between non-power-of-2 levels of multilevel memory cells and 2-level data bits
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US Patent 7433234 Floating-body cell (FBC) semiconductor storage device having a buried electrode serving as gate electrode, and a surface electrode serving as plate electrode
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US Patent 7436725 Data generator having stable duration from trigger arrival to data output start
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US Patent 7440329 Floating body cell (FBC) memory device with a sense amplifier for refreshing dummy cells
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US Patent 7443736 Substrate electron injection techniques for programming non-volatile charge storage memory cells and for controlling program disturb
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US Patent 7447070 Highly compact non-volatile memory and method therefor with internal serial buses
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US Patent 7447073 Method for handling a defective top gate of a source-side injection flash memory array
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US Patent 7447092 Write driver circuit for controlling a write current applied to a phase change memory based on an ambient temperature
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US Patent 7447108 Output controller for controlling data output of a synchronous semiconductor memory device
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US Patent 7450429 Method and apparatus for a dual power supply to embedded non-volatile memory
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US Patent 7450456 Temperature determination and communication for multiple devices of a memory module
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US Patent 7457155 Non-volatile memory device and method having bit-state assignments selected to minimize signal coupling
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US Patent 7457171 Integrated semiconductor memory with transmission of data via a data interface
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US Patent 7460395 Thyristor-based semiconductor memory and memory array with data refresh
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US Patent 7460401 Method for checking block erasing of a memory and circuit thereof
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US Patent 7463536 Memory array incorporating two data busses for memory array block selection
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US Patent 7466593 Non-volatile semiconductor memory device reading and writing multi-value data defined by a combination of different data levels of cells
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US Patent 7468900 Semiconductor memory device having a bitline amplified to a positive voltage and a negative voltage
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US Patent 7471548 Structure of static random access memory with stress engineering for stability
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US Patent 7474559 Circuit and method for employing unused configuration memory cells as scratchpad memory
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US Patent 7480199 Method for low power refresh of a dynamic random access memory using a slower refresh rate than a normal refresh rate
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US Patent 7483286 Semiconductor memory device with high permeability lines interposed between adjacent transmission lines
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US Patent 7486550 Semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell
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US Patent 7489555 Program-verify sensing for a multi-level cell (MLC) flash memory device
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US Patent 7489587 Semiconductor memory device capable of controlling clock cycle time for reduced power consumption
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US Patent 7489588 Semiconductor memory device having a main amplifier equipped with a current control circuit in a burst read operation
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US Patent 7495954 Method for partitioned erase and erase verification to compensate for capacitive coupling effects in non-volatile memory
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US Patent 7495974 Delay selecting circuit for semiconductor memory device
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US Patent 7499317 System for partitioned erase and erase verification in a non-volatile memory to compensate for capacitive coupling
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US Patent 7499318 Nonvolatile semiconductor memory device having a management memory capable of suppressing bitline interference during a read operation
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US Patent 7499332 Circuit and method for electrically programming a non-volatile semiconductor memory via an additional programming pulse after verification
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US Patent 7499371 Semiconductor memory system with a variable and settable preamble f
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US Patent 7505312 Nonvolatile semiconductor memory device capable of controlling proximity effect due to coupling between adjacent charge storage layers
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US Patent 7518898 Semiconductor memory device with strengthened power and method of strengthening power of the same
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US Patent 7518904 Method of resetting phase change memory bits through a series of pulses of increasing amplitude
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US Patent 7525840 Memory array with pseudo single bit memory cell and method
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US Patent 7529144 Hierarchical semiconductor memory device capable of carrying out a disturb refresh test on a memory array basis
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US Patent 7535777 Driving signal generator for bit line sense amplifier driver
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US Patent 7539074 Protection circuit with antifuse configured as semiconductor memory redundancy circuitry
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US Patent 7542334 Bistable latch circuit implemented with nanotube-based switching elements
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US Patent 7545668 Mushroom phase change memory having a multilayer electrode
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US Patent 7548477 Method and apparatus for adapting circuit components of a memory module to changing operating conditions
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US Patent 7554852 Method of erasing flash memory with pre-programming memory cells only in the presence of a cell leakage
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US Patent 7561471 Cycling improvement using higher erase bias
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US Patent 7567458 Flash memory array having control/decode circuitry for disabling top gates of defective memory cells
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US Patent 7567477 Bias sensing in sense amplifiers through a voltage-coupling/decoupling device
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US Patent 7570516 Three-dimensional semiconductor memory device having a first and second charge accumulation region
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US Patent 7570524 Circuitry for reading phase change memory cells having a clamping circuit
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US Patent 7573755 Data amplifying circuit for semiconductor integrated circuit
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US Patent 7573758 Phase-change random access memory (PRAM) performing program loop operation and method of programming the same
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US Patent 7573769 Enable signal generator counteracting delay variations for producing a constant sense amplifier enable signal and methods thereof
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US Patent 7573775 Setting threshold voltages of cells in a memory block to reduce leakage in the memory block
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US Patent 7577044 Resistive memory element sensing using averaging
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US Patent 7583526 Random access memory including nanotube switching elements
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US Patent 7593265 Low noise sense amplifier array and method for nonvolatile memory
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US Patent 7596020 Multi-level nonvolatile semiconductor memory device capable of discretely controlling a charge storage layer potential based upon accumulated electrons
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US Patent 7599245 Output controller capable of generating only necessary control signals based on an activated selection signal
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US Patent 7606059 Three-dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array
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US Patent 7606087 Semiconductor memory device and over driving method thereof
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US Patent 7606095 Semiconductor memory device having a precharge voltage supply circuit capable of reducing leakage current between a bit line and a word line in a power-down mode
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US Patent 7613046 Nonvolatile semiconductor memory device carrying out simultaneous programming of memory cells
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US Patent 7619947 Integrated circuit having a supply voltage controller capable of floating a variable supply voltage
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US Patent RE41019 Multi-state EEPROM having write-verify control circuit
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US Patent RE41020 Multi-state EEPROM having write-verify control circuit
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US Patent RE41021 Multi-state EEPROM having write-verify control circuit
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US Patent 7626861 Employing unused configuration memory cells as scratchpad memory
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US Patent 7626863 Flash memory array system including a top gate memory cell
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US Patent 7636264 Single-ended sense amplifier for very low voltage applications
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US Patent 7639551 Sense amplifiers operated under hamming distance methodology
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US Patent 7639558 Phase change random access memory (PRAM) device
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US Patent 7649793 Channel estimation for multi-level memories using pilot signals
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US Patent 7652908 Ferroelectric memory having a refresh control circuit capable of recovering residual polarization of unselected memory cells
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US Patent 7656738 Nonvolatile semiconductor storage device having a low resistance write-bit-line and a low capacitance read-bit-line pair
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US Patent 7660182 Extraction and stabilization of a binary code based on physical parameters of an integrated circuit
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US Patent 7663909 Integrated circuit having a phase change memory cell including a narrow active region width
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US Patent 7663921 Flash memory array with a top gate line dynamically coupled to a word line
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US Patent 7668024 Hybrid static and dynamic sensing for memory arrays
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US Patent 7668038 Semiconductor memory device including a write recovery time control circuit
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US Patent 7672179 System and method for driving a memory circuit using a pull-up resistance for inhibiting a voltage decay on a transmission line
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US Patent 7675765 Phase-change memory (PCM) based universal content-addressable memory (CAM) configured as binary/ternary CAM
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US Patent 7675780 Program time adjustment as function of program voltage for improved programming speed in memory system
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US Patent 7679964 Semiconductor memory device controlling program voltage according to the number of cells to be programmed and method of programming the same
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US Patent 7679969 Semiconductor memory device utilizing data mask signal for sharing an input/output channel in a test mode and data output method using the same
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US Patent 7684264 Memory system with RAM array and redundant RAM memory cells having a different designed cell circuit topology than cells of non redundant RAM array
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US Patent 7688632 Nonvolatile semiconductor memory capable of trimming an initial program voltage for each word line
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US Patent 7688659 Semiconductor memory capable of testing a failure before programming a fuse circuit and method thereof
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US Patent 7692951 Resistance change memory device with a variable resistance element formed of a first and a second composite compound
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US Patent 7692961 Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
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US Patent 7692983 Memory system mounted directly on board and associated method
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US Patent 7697324 Non-volatile memory device and method having bit-state assignments selected to minimize signal coupling
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US Patent RE41244 Multi-state EEPROM having write-verify control circuit
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US Patent 7706182 Adaptive programming of analog memory cells using statistical characteristics
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US Patent 7706190 Method of program-verifying a nonvolatile memory device using subdivided verifications with increasing verify voltages
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US Patent 7706205 Static memory cell having independent data holding voltage
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US Patent 7706209 Semiconductor memory device capable of driving non-selected word lines to a variable negative potential based on a bank access operation
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US Patent 7710785 Semiconductor memory device having a floating storage bulk region capable of holding/emitting excessive majority carriers
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US Patent 7715244 Non-volatile register having a memory element and register logic vertically configured on a substrate
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US Patent 7715247 One-time programmable read-only memory with a time-domain sensing scheme
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US Patent 7715249 Semiconductor memory having an output driver equipped with a threshold voltage detecting circuit for adapting the drive capability thereof
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US Patent 7715250 Circuitry and method for indicating a memory
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US Patent 7719872 Write-once nonvolatile memory with redundancy capability
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US Patent 7719888 Memory device having a negatively ramping dynamic pass voltage for reducing read-disturb effect
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US Patent 7719904 Data input circuit for a semiconductor memory capable of adapting to a phase skew between a data strobe signal and an external clock signal
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US Patent 7724585 Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability
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US Patent 7724586 Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability with minimized area usage
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US Patent 7729174 Nonvolatile memory device having a bit line select voltage generator adapted to a temperature change
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US Patent 7729181 Semiconductor storage device using a bitline GND sensing scheme for a reduced real estate of pre-sense amplifier
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US Patent 7729197 Memory device having a delay locked loop with frequency control
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US Patent 7751249 Minimizing power noise during sensing in memory device
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US Patent 7751250 Memory device with power noise minimization during sensing
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US Patent 7751252 Semiconductor memory with a reference current generating circuit having a reference current generating section and an amplifier section
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US Patent 7755966 Memory device performing a partial refresh operation based on accessed and/or refreshed memory blocks and method thereof
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US Patent 7760550 Methods of reading data from non-volatile semiconductor memory device
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US Patent RE41456 Multi-state EEPROM having write-verify control circuit
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US Patent RE41468 Multi-state EEPROM having write-verify control circuit
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US Patent 7768826 Methods for partitioned erase and erase verification in non-volatile memory to compensate for capacitive coupling effects
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US Patent 7768857 Method of refreshing data in a storage location based on heat dissipation level and system thereof
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US Patent RE41485 Multi-state EEPROM having write-verify control circuit
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US Patent 7773412 Method and apparatus for providing a non-volatile memory with reduced cell capacitive coupling
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US Patent 7773415 Flash memory device capable of preventing soft-programming during a read operation and reading method thereof
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US Patent 7778080 Flash memory array system including a top gate memory cell
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US Patent 7782652 Volatile nanotube-based switching elements with multiple controls
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US Patent 7782706 Semiconductor memory device having a word line activation circuit and/or a bit line activation circuit and a redundant word line activation circuit and/or a redundant bit line acitvation circuit
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US Patent 7787311 Memory with programmable address strides for accessing and precharging during the same access cycle
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US Patent 7791969 Method and apparatus for screening bit line of a static random access memory (SRAM) for excessive leakage current
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US Patent RE41733 Dual-addressed rectifier storage device
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US Patent 7808829 Flash memory device capable of overcoming fast program/slow erase phenomenon and erase method thereof
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US Patent 7813177 Analog single-poly EEPROM incorporating two tunneling regions for programming the memory device
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US Patent 7821806 Nonvolatile semiconductor memory circuit utilizing a MIS transistor as a memory cell
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US Patent 7821838 Method for erasing/programming/correcting a multi-level cell (MLC)
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US Patent 7826249 Three dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array
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US Patent 7826266 Semiconductor device having global and local data lines coupled to memory mats
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US Patent 7826282 Random access memory for use in an emulation environment
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US Patent 7830727 Apparatus and method for low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines
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US Patent RE41950 Multi-state EEPROM having write-verify control circuit
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US Patent 7839673 Thin-film memory system having thin-film peripheral circuit and memory controller for interfacing with a standalone thin-film memory
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US Patent 7839702 Three-dimensional non-volatile register with an oxygen-ion-based memory element and a vertically-stacked register logic
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US Patent RE41969 Multi-state EEPROM having write-verify control circuit
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US Patent 7848128 Apparatus and method for implementing matrix-based search capability in content addressable memory devices
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US Patent 7848140 Flash memory array system including a top gate memory cell
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US Patent 7852668 Semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell
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US Patent 7852707 Data output control circuit of a double data rate (DDR) synchronous semiconductor memory device responsive to a delay locked loop (DLL) clock
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US Patent 7855920 Semiconductor memory device having a floating storage bulk region capable of holding/emitting excessive majority carriers
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US Patent 7859921 Apparatus and method for low power sensing in a multi-port SRAM using pre-discharged bit lines
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US Patent 7859925 Anti-fuse latch self-test circuit and method
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US Patent 7864584 Expanded programming window for non-volatile multilevel memory cells
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US Patent 7869245 Semiconductor storage device with first and second pads arranged in proximity with first to fourth output transistors for reducing an excess region
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US Patent 7869250 ROM semiconductor integrated circuit device having a plurality of common source lines
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US Patent 7869280 Semiconductor memory device realizing a channel voltage control scheme adopting dummy cells with threshold voltage higher than threshold voltage of erased memory cells and method thereof
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US Patent 7876616 System and method for wear leveling utilizing a relative wear counter
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US Patent 7876627 Semiconductor memory device having a sense amplifier circuit with decreased offset
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US Patent 7881116 Nonvolatile semiconductor memory capable of trimming an initial program voltage for each word line
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US Patent RE42120 Multi-state EEPROM having write-verify control circuit
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US Patent 7885131 Resistance change semiconductor memory device and method of reading data with a first and second switch circuit
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US Patent 7889555 Flash memory system capable of operating in a random access mode and data reading method thereof
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US Patent 7894256 Thyristor based memory cell
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US Patent 7894259 Nonvolatile semiconductor memory device with first and second write sequences controlled by a command or an address
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US Patent 7894280 Asymmetrical SRAM cell with separate word lines
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US Patent 7894287 Semiconductor memory device controlling a voltage supplied to a dummy bit line
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US Patent 7898870 Nonvolatile memory device having a bit line select voltage generator adapted to a temperature change
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US Patent 7898882 Architecture, system and method for compressing repair data in an integrated circuit (IC) design
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US Patent 7898901 Method for controlling clock cycle time for reduced power consumption in a semiconductor memory device
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US Patent 7903467 Programming method of multi-bit flash memory device for reducing programming error
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US Patent 7903488 Bias sensing in DRAM sense amplifiers through voltage-coupling/decoupling device
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US Patent 7903497 Multi-port SRAM implemented with single-port 6-transistor memory cells coupled to an input multiplexer and an output demultiplexer
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US Patent 7907468 Memory device having data paths permitting array/port consolidation and swapping
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US Patent 7916556 Semiconductor memory device, sense amplifier circuit and memory cell reading method using a threshold correction circuitry
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US Patent 7916573 Word line block/select circuit with repair address decision unit
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US Patent 7920439 Semiconductor memory device using a bandgap reference circuit and a reference voltage generator for operating under a low power supply voltage
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US Patent 7924588 Content addressable memory with concurrent two-dimensional search capability in both row and column directions
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US Patent 7924622 Flash memory device and operating method for concurrently applying different bias voltages to dummy memory cells and regular memory cells during erasure
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US Patent 7924623 Method for memory cell erasure with a programming monitor of reference cells
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US Patent RE42310 Dual-addressed rectifier storage device
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US Patent 7933161 Memory device configured to refresh memory cells in a power-down state
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US Patent 7936599 Coarse and fine programming in a solid state memory
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US Patent 7936600 Methods of programming data in a non-volatile memory device with a fringe voltage applied to conductive layer
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US Patent 7936630 Method and apparatus for calibrating a read/write channel in a memory arrangement
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US Patent 7940581 Method for low power sensing in a multi-port SRAM using pre-discharged bit lines
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US Patent 7944735 Method of making a nanotube-based shadow random access memory
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US Patent 7944773 Synchronous command-based write recovery time auto-precharge control
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US Patent 7948795 Thin film magnetic memory device including memory cells having a magnetic tunnel junction
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US Patent 7952922 Method for programming a non-volatile memory device to reduce floating-gate-to-floating-gate coupling effect
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US Patent 7957197 Nonvolatile memory with a current sense amplifier having a precharge circuit and a transfer gate coupled to a sense node
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US Patent 7961529 Processor including vertically stacked third-dimensional embedded re-writeable non-volatile memory and registers
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US Patent 7961531 Voltage sensing circuit capable of controlling a pump voltage stably generated in a low voltage environment
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US Patent 7965561 Row selector occupying a reduced device area for semiconductor memory devices
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US Patent 7969777 Thyristor-based memory array having lines with standby voltages
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US Patent 7974149 Thin-film memory system equipped with a thin-film address decoder and memory controller
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US Patent 7978526 Low noise sense amplifier array and method for nonvolatile memory
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US Patent 7978540 Extraction of a binary code based on physical parameters of an integrated circuit via programming resistors
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US Patent 7978560 Static memory cell having independent data holding voltage
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US Patent 7983089 Sense amplifier with capacitance-coupled differential sense amplifier
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US Patent 7986571 Low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines
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US Patent 7986572 Magnetic memory capable of minimizing gate voltage stress in unselected memory cells
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US Patent 7995385 Memory array of pairs of nonvolatile memory cells using Fowler-Nordheim programming and erasing
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US Patent 7995402 Method for erasing a semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell
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US Patent 7995405 Semiconductor memory device having a sense amplifier circuit with decreased offset
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US Patent 7995408 Circuit for supplying a reference voltage in a semiconductor memory device for testing an internal voltage generator therein
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US Patent 7995421 Semiconductor memory device with a sense amplifier controller for maintaining the connection of a previously selected memory cell array
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US Patent 8000156 Memory device with propagation circuitry in each sub-array and method thereof
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US Patent 8000160 Semiconductor device and cell plate voltage generating apparatus thereof
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US Patent 8000160 Semiconductor device and cell plate voltage generating apparatus thereof
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US Patent 8000156 Memory device with propagation circuitry in each sub-array and method thereof
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US Patent 7995405 Semiconductor memory device having a sense amplifier circuit with decreased offset
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US Patent 7986572 Magnetic memory capable of minimizing gate voltage stress in unselected memory cells
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edited on 8 Dec, 2021
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US Patent 7986571 Low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines
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edited on 8 Dec, 2021
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Infobox (+1 properties)
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Patent primary examiner of
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US Patent 7983089 Sense amplifier with capacitance-coupled differential sense amplifier
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edited on 8 Dec, 2021
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US Patent 7978560 Static memory cell having independent data holding voltage
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US Patent 7978526 Low noise sense amplifier array and method for nonvolatile memory
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US Patent 7974149 Thin-film memory system equipped with a thin-film address decoder and memory controller
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US Patent 7969777 Thyristor-based memory array having lines with standby voltages
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US Patent 7965561 Row selector occupying a reduced device area for semiconductor memory devices
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