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Amir Zarabian

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edited on 14 Dec, 2021
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Patent primary examiner of
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US Patent 7087509 Method of forming a gate electrode on a semiconductor device and a device incorporating same
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US Patent 7088637 Semiconductor memory device for high speed data access
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US Patent 7092276 Series feram cell array
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US Patent 7092278 Memory device
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US Patent 7095640 Multiple match detection circuit and method
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US Patent 7095651 Non-volatile semiconductor memory device
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US Patent 7095667 Noise resistant small signal sensing circuit for a memory device
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US Patent 7095674 Modular register array
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US Patent 7099177 Nonvolatile ferroelectric memory device having power control function
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US Patent 7099179 Conductive memory array having page mode and burst mode write capability
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US Patent 7099188 Bit line reference circuits for binary and multiple-bit-per-cell memories
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US Patent 7099193 Nonvolatile semiconductor memory device, electronic card and electronic apparatus
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US Patent 7099213 Page buffer for flash memory device
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US Patent 7099219 Multi read port bit line
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US Patent 7102904 System and method for minimizing noise on a dynamic node
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US Patent 7102912 Integrated semiconductor memory device and method for operating an integrated semiconductor memory device
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US Patent 7102917 Memory array method and system
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US Patent 7102922 Thin film magnetic memory device capable of conducting stable data read and write operations
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US Patent 7102930 Method of programming a non-volatile memory cell to eliminate or to minimize program deceleration
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US Patent 7102935 Semiconductor memory device driven with low voltage
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US Patent 7102955 Reduction of fusible links and associated circuitry on memory dies
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US Patent 7102956 Reduction of fusible links and associated circuitry on memory dies
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US Patent 7102957 Reduction of fusible links and associated circuitry on memory dies
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US Patent 7102959 Synchronous semiconductor memory device of fast random cycle system and test method thereof
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US Patent 7106639 Defect management enabled PIRM and method
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US Patent 7110288 Thin film magnetic memory device having redundant configuration
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US Patent 7110321 Multi-bank integrated circuit memory devices having high-speed memory access timing
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US Patent 7113419 Ferroelectric memory device and method of reading a ferroelectric memory
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US Patent 7113425 Nonvolatile semiconductor memory device with scalable two transistor memory cells
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US Patent 7115480 Micromechanical strained semiconductor by wafer bonding
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US Patent 7116570 Access circuit and method for allowing external test voltage to be applied to isolated wells
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US Patent 7116578 Non-volatile memory device and data storing method
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US Patent 7116594 Sense amplifier circuits and high speed latch circuits using gated diodes
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US Patent 7116604 Semiconductor memory device and method for selecting multiple word lines in a semiconductor memory device
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US Patent 7120042 Ferroelectric memory device having test memory cell
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US Patent 7120043 FeRAM having single ended sensing architecture
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US Patent 7120063 Flash memory cell and methods for programming and erasing
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US Patent 7120077 Memory module having a plurality of integrated memory components
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US Patent 7120080 Dual port semiconductor memory device
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US Patent 7122401 Area array type semiconductor package fabrication method
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US Patent 7123514 Memory device for improved reference current configuration
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US Patent 7123531 Differential amplifier and bit-line sense amplifier adopting the same
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US Patent 7126840 Ferroelectric memory device and electronic apparatus
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US Patent 7126862 Decoder for memory device
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US Patent 7126873 Method and system for expanding flash storage device capacity
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US Patent 7136302 Integrated circuit memory device and method
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US Patent 7136306 Single bit nonvolatile memory cell and methods for programming and erasing thereof
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US Patent 7139194 Nonvolatile semiconductor memory
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US Patent 7142445 Ferroelectric memory device, method of driving the same, and driver circuit
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US Patent 7142465 Semiconductor memory
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US Patent 7145807 Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories
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US Patent 7145822 Method and apparatus for optimal write restore for memory
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US Patent 7149112 Semiconductor memory device with signal lines arranged across memory cell array thereof
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US Patent 7149136 Memory circuit with redundant memory cell array allowing simplified shipment tests and reduced power consumptions
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US Patent 7154766 Ferroelectric memory
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US Patent 7154776 Thin film magnetic memory device writing data with bidirectional current
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US Patent 7154789 High-voltage generator circuit and semiconductor memory device including the same
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US Patent 7154795 Clock signal initiated precharge technique for active memory subarrays in dynamic random access memory (DRAM) devices and other integrated circuit devices incorporating embedded DRAM
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US Patent 7154808 Semiconductor memory device for simultaneously testing blocks of cells
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US Patent 7158402 Asymmetric static random access memory device having reduced bit line leakage
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US Patent 7158436 Semiconductor memory devices
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US Patent 7158443 Delay-lock loop and method adapting itself to operate over a wide frequency range
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US Patent 7161839 Non-volatile memory device and program method thereof
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US Patent 7161865 Semiconductor device
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US Patent 7161868 Multiport semiconductor memory device capable of sufficiently steadily holding data and providing a sufficient write margin
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US Patent 7164603 Operation scheme with high work function gate and charge balancing for charge trapping non-volatile memory
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US Patent 7164614 Fuse box, semiconductor memory device having the same and setting method thereof
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US Patent 7167392 Non-volatile memory cell with improved programming technique
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US Patent 7167408 Circuitry for a programmable element
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US Patent 7170776 Non-volatile memory device conducting comparison operation
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US Patent 7170783 Layout for NAND flash memory array having reduced word line impedance
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US Patent 7170784 Non-volatile memory and method with control gate compensation for source line bias errors
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US Patent 7170785 Method and apparatus for operating a string of charge trapping memory cells
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US Patent 7170794 Programming method of a non-volatile memory device having a charge storage layer between a gate electrode and a semiconductor substrate
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US Patent 7170795 Electrically erasable charge trap nonvolatile memory cells having erase threshold voltage that is higher than an initial threshold voltage
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US Patent 7170805 Memory devices having bit line precharge circuits with off current precharge control and associated bit line precharge methods
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US Patent 7170807 Data storage device and refreshing method for use with such device
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US Patent 7170814 Multi-port semiconductor memory
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US Patent 7170815 Memory apparatus having multi-port architecture for supporting multi processor
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US Patent 7173837 Content addressable memory (CAM) cell bit line architecture
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US Patent 7173838 Content addressable memory device
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US Patent 7173854 Non-volatile memory and method with compensation for source line bias errors
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US Patent 7173866 Circuit for generating data strobe signal in DDR memory device, and method therefor
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US Patent 7173873 Device and method for breaking leakage current path
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US Patent 7177176 Six-transistor (6T) static random access memory (SRAM) with dynamically variable p-channel metal oxide semiconductor (PMOS) strength
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US Patent 7177204 Pulse width adjusting circuit for use in semiconductor memory device and method therefor
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US Patent 7177209 Semiconductor memory device and method of driving the same
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US Patent 7177222 Reducing power consumption in a data storage system
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US Patent 7180798 Semiconductor physical quantity sensing device
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US Patent 7180809 Refresh control circuit of pseudo SRAM
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US Patent 7180821 Memory device, memory controller and memory system having bidirectional clock lines
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US Patent 7180824 Semiconductor memory device with a page mode
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US Patent 7184293 Crosspoint-type ferroelectric memory
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US Patent 7184296 Memory device
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US Patent 7184297 Semiconductor memory device
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US Patent 7184311 Method and system for regulating a program voltage value during multilevel memory device programming
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US Patent 7184322 Semiconductor memory device and control method thereof
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US Patent 7184323 4N pre-fetch memory data transfer system
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US Patent 7184332 Memory circuit and method for processing a code to be loaded into a memory circuit
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US Patent 7184346 Memory cell sensing with low noise generation
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US Patent 7184353 Semiconductor device
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US Patent 7184358 Semiconductor memory
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US Patent 7187587 Programmable memory address and decode circuits with low tunnel barrier interpoly insulators
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US Patent 7190604 Capacity dividable memory IC
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US Patent 7190612 Circuitry for use in current switching a magnetic cell
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US Patent 7193886 Integrated circuit with a memory of reduced consumption
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US Patent 7193887 SRAM circuitry
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US Patent 7193897 NAND flash memory device capable of changing a block size
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US Patent 7193912 Semiconductor integrated circuit device
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US Patent 7193915 Semiconductor memory device
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US Patent 7193924 Dual-port static random access memory having improved cell stability and write margin
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US Patent 7196948 Method and apparatus for data capture on a bi-directional bus
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US Patent 7196956 Semiconductor memory device changing refresh interval depending on temperature
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US Patent 7200052 Apparatus and methods for regulated voltage
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US Patent 7200056 Memory row/column replacement in an integrated circuit
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US Patent 7203085 Semiconductor integrated circuit
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US Patent 7203088 Magnetoresistive random access memory and driving method thereof
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US Patent 7203091 Semiconductor integrated circuit device and non-volatile memory system using the same
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US Patent 7203110 Precharge circuit and method employing inactive weak precharging and equalizing scheme and memory device including the same
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US Patent 7203121 Semiconductor integrated circuit device and data write method thereof
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US Patent 7206228 Block switch in flash memory device
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US Patent 7206230 Use of data latches in cache operations of non-volatile memories
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US Patent 7206241 Semiconductor device and programming method
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US Patent 7206242 Semiconductor memory
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US Patent 7206244 Temperature based DRAM refresh
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US Patent 7206251 Dual port PLD embedded memory block to support read-before-write in one clock cycle
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US Patent 7209398 Semiconductor memory device having redundancy cell array shared by a plurality of memory cell arrays
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US Patent 7212430 Semiconductor memory
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US Patent 7212435 Minimizing adjacent wordline disturb in a memory device
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US Patent 7212437 Charge coupled EEPROM device and corresponding method of operation
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US Patent 7212444 Semiconductor nonvolatile memory device
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US Patent 7215562 Semiconductor storage device
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US Patent 7215577 Flash memory cell and methods for programming and erasing
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US Patent 7215594 Address latch circuit of memory device
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US Patent 7221592 Multiple level programming in a non-volatile memory device
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US Patent 7224616 Circuit and method for generating wordline voltage in nonvolatile semiconductor memory device
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US Patent 7224618 Nonvolatile semiconductor memory device with erase voltage measurement
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US Patent 7224624 Page buffer for nonvolatile semiconductor memory device and method of operation
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US Patent 7224631 Non-skipping auto-refresh in a DRAM
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US Patent 7227769 Semiconductor memory
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US Patent 7227774 MRAM integrated circuits, MRAM circuits, and systems for testing MRAM integrated circuits
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US Patent 7227787 Method for erasing an NROM cell
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US Patent 7227791 Semiconductor memory device including circuit to store access data
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US Patent 7233520 Process for erasing chalcogenide variable resistance memory bits
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US Patent 7233522 NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same
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US Patent 7233529 System for erasing nonvolatile memory
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US Patent 7236410 Memory cell driver circuits
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US Patent 7239554 Nonvolatile memory device and method of improving programming characteristic
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US Patent 7239558 Method of hot electron injection programming of a non-volatile memory (NVM) cell array in a single cycle
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US Patent 7239564 Semiconductor device for rectifying memory defects
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US Patent 7239570 Magnetic memory device and method for magnetic reading and writing
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US Patent 7242602 Semiconductor memory devices having conductive line in twisted areas of twisted bit line pairs
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US Patent 7242611 Nonvolatile semiconductor memory device for writing multivalued data
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US Patent 7248499 Layout for NAND flash memory array having reduced word line impedance
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US Patent 7248502 Non-volatile semiconductor memory device
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US Patent 7248514 Semiconductor memory device
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US Patent 7248520 Semiconductor memory and data read method of the same
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US Patent 7248525 Semiconductor memory device and refresh method for the same
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US Patent 7251157 Semiconductor device
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US Patent 7251171 Semiconductor memory and system apparatus
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US Patent 7251172 Efficient register for additive latency in DDR2 mode of operation
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US Patent 7254066 Memory device with different termination units for different signal frequencies
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US Patent 7254070 Semiconductor memory device with redundancy circuit
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US Patent 7254072 Semiconductor memory device having hierarchically structured data lines and precharging means
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US Patent 7254084 Data processing device
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US Patent 7257020 Thin film magnetic memory device having redundant configuration
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US Patent 7257024 Minimizing adjacent wordline disturb in a memory device
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US Patent 7260009 Semiconductor integrated circuit
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US Patent 7260013 Power supply device in semiconductor memory
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US Patent 7262990 Semiconductor memory device
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US Patent 7262999 System and method for preventing read margin degradation for a memory array
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US Patent 7266027 Integrated semiconduct memory with test circuit
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US Patent 7269064 Method of controlling page buffer having dual register and circuit thereof
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US Patent 7269074 Semiconductor storage device and semiconductor storage device driving method
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US Patent 7269081 Program circuit of semiconductor
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US Patent 7272029 Transition-encoder sense amplifier
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US Patent 7272039 Minimizing adjacent wordline disturb in a memory device
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US Patent 7272047 Wordline voltage generating circuit including a voltage dividing circuit for reducing effects of parasitic capacitance
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US Patent 7272054 Time domain bridging circuitry for use in determining output enable timing
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US Patent 7272060 Method, system, and circuit for performing a memory related operation
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US Patent 7274586 Method for programming phase-change memory array to set state and circuit of a phase-change memory device
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US Patent 7274609 High speed redundant data sensing method and apparatus
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US Patent 7274614 Flash cell fuse circuit and method of fusing a flash cell
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US Patent 7277317 MRAM architecture for low power consumption and high selectivity
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US Patent 7277336 Method and apparatus for improving yield in semiconductor devices by guaranteeing health of redundancy information
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US Patent 7280383 Semiconductor memory device and a method for arranging signal lines thereof
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US Patent 7280388 MRAM with a write driver and method therefor
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US Patent 7283405 Semiconductor memory device and signal processing system
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US Patent 7283406 High voltage wordline driver with a three stage level shifter
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US Patent 7283417 Write control circuitry and method for a memory array configured with multiple memory subarrays
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US Patent 7289350 Electronic device with a memory cell
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US Patent 7289362 Erasable and programmable non-volatile cell
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US Patent 7289363 Memory cell repair using fuse programming method in a flash memory device
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US Patent 7289367 Semiconductor memory device capable of carrying out stable operation
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US Patent 7289383 Reducing the number of power and ground pins required to drive address signals to memory modules
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US Patent 7292475 Nonvolatile memory device and data write method for nonvolatile memory device
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US Patent 7292486 Methods and circuits for latency control in accessing memory devices
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US Patent 7292488 Temperature dependent self-refresh module for a memory device
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US Patent 7295470 Non-volatile memory device including multi-page copyback system and method
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US Patent 7298666 Device for distributing input data for memory device
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US Patent 7301820 Non-volatile memory dynamic operations
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US Patent 7301835 Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability
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US Patent 7301840 Semiconductor memory device
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US Patent 7301848 Apparatus and method for supplying power in semiconductor device
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US Patent 7307869 Method and circuit for reading a dynamic memory circuit
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US Patent 7310261 Nitride read-only memory (NROM) device and method for reading the same
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US Patent 7310272 System for performing data pattern sensitivity compensation using different voltage
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US Patent 7313019 Step voltage generation
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US Patent 7313024 Non-volatile memory device having page buffer for verifying pre-erase
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US Patent 7317634 Nonvolatile semiconductor memory device
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US Patent 7319611 Bitline transistor architecture for flash memory
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US Patent 7319631 Semiconductor memory device with a stacked-bank architecture and method for driving word lines of the same
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US Patent 7321518 Apparatus and methods for providing redundancy in integrated circuits
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US Patent 7324377 Apparatus and method for programming and erasing virtual ground EEPROM without disturbing adjacent cells
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US Patent 7327593 ROM memory cell having defined bit line voltages
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US Patent 7327594 Read-only memory with twisted bit lines
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US Patent 7327610 DRAM memory with common pre-charger
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US Patent 7327616 Non-volatile semiconductor memory device
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US Patent 7333374 Semiconductor memory device capable of replacing defective memory cell with redundant memory cell, and electronic equipment
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US Patent 7336546 Global bit select circuit with dual read and write bit line pairs
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US Patent 7336555 Refresh control circuit of pseudo SRAM
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US Patent 7336558 Semiconductor memory device with reduced number of pads
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US Patent 7339850 Semiconductor memory device allowing high-speed data reading
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US Patent 7342842 Data storage device and refreshing method for use with such device
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US Patent 7345916 Method and apparatus for high voltage operation for a high performance semiconductor memory device
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US Patent 7345931 Maintaining internal voltages of an integrated circuit in response to a clocked standby mode
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US Patent 7345933 Qualified data strobe signal for double data rate memory controller module
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US Patent 7345946 Dual-voltage wordline drive circuit with two stage discharge
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US Patent 7349241 SRAM circuitry
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US Patent 7349263 Circuit and method for adaptive incremental step-pulse programming in a flash memory device
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US Patent 7349264 Alternate sensing techniques for non-volatile memories
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US Patent 7352632 Non-volatile semiconductor memory device
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US Patent 7352636 Circuit and method for generating boosted voltage in semiconductor memory device
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US Patent 7352644 Semiconductor memory with reset function
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US Patent 7352646 Semiconductor memory device and method of arranging a decoupling capacitor thereof
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US Patent 7359256 Semiconductor memory device
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US Patent 7362622 System for determining a reference level and evaluating a signal on the basis of the reference level
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US Patent 7362628 Semiconductor memory and redundancy repair method
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US Patent 7362634 Built-in system and method for testing integrated circuit timing parameters
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US Patent 7366035 Ferroelectric memory and method of driving the same
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US Patent 7366036 Memory device with control circuit for regulating power supply voltage
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US Patent 7366038 Circuit and method of driving a word line of a memory device
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US Patent 7372736 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
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US Patent 7372756 Non-skipping auto-refresh in a DRAM
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US Patent 7385836 Ferroelectric random access memory
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US Patent 7391645 Non-volatile memory and method with compensation for source line bias errors
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US Patent 7391646 Non-volatile memory and method with control gate compensation for source line bias errors
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US Patent 7391654 Memory block erasing in a flash memory device
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US Patent 7391668 Integrated circuit device and electronic device
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US Patent 7394683 Solid state magnetic memory system and method
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US Patent 7414908 Magnetic memory device
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US Patent 7453756 Method for powering an electronic device and circuit
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US Patent 7460394 Phase change memory having temperature budget sensor
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US Patent 7463508 SRAM test method and SRAM test arrangement to detect weak cells
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US Patent 7463539 Method for burst mode, bit line charge transfer and memory using the same
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US Patent 7463541 Semiconductor storage device
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US Patent 7466591 Method for programming and erasing an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits
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US Patent 7471543 Storage device and semiconductor device
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US Patent 7471545 Semiconductor memory device
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US Patent 7471551 Magnetic memory
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US Patent 7471570 Embedded EEPROM array techniques for higher density
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US Patent 7474556 Phase-change random access memory device
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US Patent 7477561 Semiconductor memory device
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US Patent 7483287 Semiconductor memory
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US Patent 7483305 Method, apparatus and system relating to automatic cell threshold voltage measurement
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US Patent 7483320 Data input/output method of semiconductor memory device and semiconductor memory device for the same
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US Patent 7486554 NAND flash memory devices having shielding lines between wordlines and selection lines
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US Patent 7486558 Non-volatile memory with managed execution of cached data
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US Patent 7486566 Methods, apparatus, and systems for flash memory bit line charging
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US Patent 7486569 Nonvolatile semiconductor memory
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US Patent 7486574 Row active control circuit of pseudo static ranom access memory
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US Patent 7489553 Non-volatile memory with improved sensing having bit-line lockout control
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US Patent 7489560 Reduction of leakage current and program disturbs in flash memory devices
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US Patent 7492640 Sensing with bit-line lockout control in non-volatile memory
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US Patent 7495962 Alternating read mode
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US Patent 7511997 Semiconductor memory device
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US Patent 11189353 Memory system and memory control method
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US Patent 7522455 Method and system for reducing soft-writing in a multi-level flash memory
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US Patent 7558116 Regulation of boost-strap node ramp rate using capacitance to counter parasitic elements in channel
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US Patent 7567459 Method of measuring a channel boosting voltage in a NAND flash memory device
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US Patent 7577016 Twin-cell semiconductor memory devices
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US Patent 7577057 Circuit and method for generating write data mask signal in synchronous semiconductor memory device
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US Patent 7606066 Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same
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US Patent 7613043 Shifting reference values to account for voltage sag
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US Patent 7613060 Methods, circuits, and systems to select memory regions
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US Patent 7616480 System that compensates for coupling based on sensing a neighbor using coupling
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US Patent 7623378 Selective programming of non-volatile memory facilitated by security fuses
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US Patent 7623386 Reducing program disturb in non-volatile storage using early source-side boosting
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US Patent 7623387 Non-volatile storage with early source-side boosting for reducing program disturb
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US Patent 7623402 Semiconductor memory device operating a self refreshing and an auto refreshing
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US Patent 7630248 System that compensates for coupling during programming
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US Patent 7630254 Starting program voltage shift with cycling of non-volatile memory
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US Patent 7633795 Magnetoresistive random access memory and its write control method
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US Patent 7633816 Semiconductor memory device, rewrite processing method therefor, and program thereof
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US Patent 7643354 Neural network model for instruments that store and retrieve sequential information
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US Patent 7643372 Semiconductor integrated circuit
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US Patent 7646627 Magnetic random access memory having improved read disturb suppression and thermal disturbance resistance
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US Patent 7646665 Semiconductor memory device and burn-in test method thereof
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US Patent 7652918 Retention margin program verification
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US Patent 7652940 Column access control apparatus having fast column access speed at read operation
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US Patent 7656703 Method for using transitional voltage during programming of non-volatile storage
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US Patent 7656710 Adaptive operations for nonvolatile memories
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US Patent 7656714 Bitline bias circuit and nor flash memory device including the bitline bias circuit
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US Patent 7656724 Semiconductor integrated circuit having data input/output circuit and method for inputting data using the same
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US Patent 7656735 Dual voltage flash memory methods
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US Patent 7660143 Multibit ROM memory
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US Patent 7660149 SRAM cell with separate read and write ports
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US Patent 7663905 Ferroelectric memory device and data read method in same
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US Patent 7663920 Memory system and data reading and generating method
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US Patent 7663922 Non-volatile semiconductor memory devices with lower and upper bit lines sharing a voltage control block, and memory cards and systems having the same
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US Patent 7663923 Semiconductor memory device and control method thereof
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US Patent 7667997 Method to improve ferroelectronic memory performance and reliability
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US Patent 7668035 Memory circuits with reduced leakage power and design structures for same
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US Patent 7668036 Apparatus for controlling GIO line and control method thereof
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US Patent 7675801 Semiconductor memory device and refresh method for the same
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US Patent 7675808 Semiconductor device
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US Patent 7701777 Semiconductor memory device
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US Patent 7706200 Internal voltage generator
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US Patent 7768866 Method and system for preventing noise disturbance in high speed, low power memory
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US Patent 7787323 Level detect circuit
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US Patent 7791930 Magnetoresistive random access memory
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US Patent 7835180 Semiconductor memory device
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US Patent 7838354 Method for patterning contact etch stop layers by using a planarization process
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US Patent 7839693 Method of fabricating CMOS-compatible non-volatile memory cell with lateral inter-poly programming layer
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US Patent 7846767 Semiconductor-on-diamond devices and associated methods
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US Patent 7852659 Time efficient phase change memory data storage device
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US Patent 7864572 Flash memory storage apparatus, flash memory controller, and switching method thereof
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US Patent 7898896 Semiconductor device
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US Patent 7911845 Non-volatile semiconductor memory device
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US Patent 7933156 Adjusting a digital delay function of a data memory unit
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US Patent 7936591 Magnetoresistive random access memory
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US Patent 7940582 Integrated circuit that stores defective memory cell addresses
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US Patent 7957206 Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same
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US Patent 7961535 Test circuit and method for use in semiconductor memory device
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US Patent 7961537 Semiconductor integrated circuit
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US Patent 7965544 Magnetic memory element, magnetic memory having said magnetic memory element, and method for driving magnetic memory
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US Patent 7940582 Integrated circuit that stores defective memory cell addresses
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US Patent 7936591 Magnetoresistive random access memory
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US Patent 7933156 Adjusting a digital delay function of a data memory unit
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US Patent 7898896 Semiconductor device
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US Patent 7864572 Flash memory storage apparatus, flash memory controller, and switching method thereof
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US Patent 7852659 Time efficient phase change memory data storage device
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US Patent 7846767 Semiconductor-on-diamond devices and associated methods
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US Patent 7838354 Method for patterning contact etch stop layers by using a planarization process
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US Patent 7791930 Magnetoresistive random access memory
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edited on 5 Dec, 2021
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US Patent 7768866 Method and system for preventing noise disturbance in high speed, low power memory
Edits on 4 Dec, 2021
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Golden AI
edited on 4 Dec, 2021
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US Patent 7706200 Internal voltage generator

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