SBIR/STTR Award attributes
Nuclear Physics experiments require reliable advanced electronics and systems functionality for next generation recording, processing, storage, distribution, and analysis of experimental data in extreme environments. Specifically, they seek new low-cost developments in detector instrumentation electronics for rad hard and cryogenic applications needing significantly improved energy, position, timing resolution, sensitivity, rate capability, stability, dynamic range, and background suppression that are not currently competitively available. Alphacore, will continue developing a full 22nm FDSOI CMOS based low-temperature operation (77K) optimized analog/mixed-signal cell library that includes: low noise charge amplifiers and filters, very high rate photoncounting circuits, high-precision charge and timing measurement circuits, low-power and small-area analog-todigital converters (ADCs), serializers, preamplifiers, filters, voltage references, and I/O circuitry. Alphacore has recently taped-out a test chip including specific low-temperature 22nm FDSOI CMOS test structures. The testchip structures will be available and can be tested at cryo temperatures during Phase I providing deep insights into the technology early in the program. A proven family of building blocks ideal for detector readout ASICs on a 22nm FDSOI technology, suitable for experiments like LEGEND and nEXO future upgrades, will enable many NP experiments of interest at national laboratories, international accelerator facilities, and universities. Alphacore will characterize 22nm FDSOI CMOS processes at very low/cryogenic temperatures. In addition to the transistor functionality, the device reliability in low temp operation environments (increased hot carrier injection, etc.) will be studied. Low-noise preamplifiers, SerDes, and other analog ADC circuits, optimized for cryogenic operation, low power dissipation, and low unit cost will be developed based on these results. Alphacore’s existing 22nm FDSOI CMOS test chip will be characterized at cryo temps in the beginning of the Phase I period. The test results will be then used to develop a comprehensive analog mixed-signal circuit block library for cryogenic operation. ASIC design in Cadence EDA tools will be prepared for fabrication in Phase II. The significance of the proposed work is that the low temperature characterization results of the selected 22nm FDSOI process, and the developed low-noise, low-power circuit block library, will provide significant cost benefits for NP experiments with newer more sensitive front end data acquisition electronics for detectors, as well as highenergy physics (HEP) experiments, such as the HL-LHC experiment at CERN with many detectors that 1) must tolerate long durations within a cryogenic chamber, and 2) will use an advanced 22nm CMOS fabrication process. Other applications that will significantly benefit are other NP experiments, defense space applications, planetary exploration missions, infrared focal plane array imaging applications in the field of missile defense and other defense applications, industrial thermal imaging, and night-time security cameras.
