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Alonzo Chambliss

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Edits on 15 Dec, 2021
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Golden AI
edited on 15 Dec, 2021
Edits made to:
Infobox (-406 properties)
Infobox
Patent primary examiner of
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US Patent 7088002 Interconnect
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US Patent 7094619 Method of fabricating a light emitting device
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US Patent 7094630 Method of fabricating semiconductor device having a chip, reinforcing plate, and sealing material sharing a common rear surface
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US Patent 7095054 Semiconductor package having light sensitive chips
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US Patent 7098117 Method of fabricating a package with substantially vertical feedthroughs for micromachined or MEMS devices
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US Patent 7101737 Method of encapsulating interconnecting units in packaged microelectronic devices
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US Patent 7102221 Memory-Module with an increased density for mounting semiconductor chips
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US Patent 7105378 Method of forming a leadframe for a semiconductor package
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US Patent 7109061 Wafer applied fluxing and underfill material, and layered electronic assemblies manufactured therewith
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US Patent 7109572 Quad flat no lead (QFN) grid array package
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US Patent 7112469 Method of fabricating a semiconductor package utilizing a thermosetting resin base member
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US Patent 7112876 Interposers and other carriers including a slot with laterally recessed area at an end thereof and semiconductor device assemblies and packages including such carriers
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US Patent 7115922 H-bridge drive utilizing a pair of high and low side MOSFET's in a common insulation housing
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US Patent 7118940 Method of fabricating an electronic package having underfill standoff
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US Patent 7119430 Spacer for mounting a chip package to a substrate
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US Patent 7122400 Method of fabricating an interconnection for chip sandwich arrangements
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US Patent 7122466 Two step semiconductor manufacturing process for copper interconnects
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US Patent 7129117 Method of embedding semiconductor chip in support plate and embedded structure thereof
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US Patent 7129150 Method of dividing a semiconductor wafer
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US Patent 7132697 Nanomaterials for quantum tunneling varistors
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US Patent 7132735 Integrated circuit package with lead fingers extending into a slot of a die paddle
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US Patent 11177188 Heat dissipation substrate for multi-chip package
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US Patent 11177198 Plurality of lead frames electrically connected to inductor chip
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US Patent 7135352 Method of fabricating a cover plate bonded over an encapsulated OLEDs
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US Patent 7138297 Method of dividing a semiconductor wafer utilizing a laser dicing technique
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US Patent 7138664 Semiconductor device having a light emitting element
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US Patent 7138673 Semiconductor package having encapsulated chip attached to a mounting plate
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US Patent 7145172 Thin film transistor array substrate
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US Patent 7145228 Microelectronic devices
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US Patent 7145236 Semiconductor device having solder bumps reliably reflow solderable
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US Patent 7153765 Method of assembling soldered packages utilizing selective solder deposition by self-assembly of nano-sized solder particles
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US Patent 7154170 Semiconductor package security features using thermochromatic inks and three-dimensional identification coding
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US Patent 7157301 Semiconductor package security features using thermochromatic inks and three-dimensional identification coding
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US Patent 7157734 Semiconductor bond pad structures and methods of manufacturing thereof
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US Patent 7161231 Semiconductor device which prevents peeling of low-permittivity film by using multilevel interconnection
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US Patent 7163842 Method of fabricating a semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA)
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US Patent 7166494 Method of fabricating a semiconductor stacked multi-package module having inverted second package
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US Patent 7166499 Method of fabricating a thin film transistor for an array panel
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US Patent 7166910 Miniature silicon condenser microphone
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US Patent 7169642 Method of fabricating a semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package
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US Patent 7170179 Chip select method through double bonding
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US Patent 7173321 Semiconductor package having multiple row of leads
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US Patent 7176059 Method of fabricating an electronic component having at least one semiconductor chip on a circuit carrier with elastic external contacts
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US Patent 7179696 Phosphorus activated NMOS using SiC process
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US Patent 7180168 Stacked semiconductor chips
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US Patent 7180181 Mesh shaped dam mounted on a substrate
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US Patent 7183623 Trimmed integrated circuits with fuse circuits
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US Patent 7189596 Process for forming a direct build-up layer on an encapsulated die packages utilizing intermediate structures
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US Patent 7198993 Method of fabricating a combined fully-depleted silicon-on-insulator (FD-SOI) and partially-depleted silicon-on-insulator (PD-SOI) devices
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US Patent 7202559 Method of assembling a ball grid array package with patterned stiffener layer
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US Patent 7202563 Semiconductor device package having a semiconductor element with resin
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US Patent 7205177 Methods of bonding two semiconductor devices
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US Patent 7205636 Semiconductor device with a multilevel interconnection connected to a guard ring
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US Patent 7205637 Semiconductor device with a multilevel interconnection connected to a guard ring and alignment mark
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US Patent 7208348 Methods of fabricating a via-in-pad with off-center geometry
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US Patent 7208361 Replacement gate process for making a semiconductor device that includes a metal gate electrode
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US Patent 7208396 Permanent adherence of the back end of a wafer to an electrical component or sub-assembly
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US Patent 7208834 Bonding structure with pillar and cap
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US Patent 7211830 Circuit interconnect for optoelectronic device
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US Patent 7211876 Semiconductor device utilizing multiple capacitors each having an insulating layer having a different thickness
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US Patent 7214585 Methods of fabricating integrated circuits with openings that allow electrical contact to conductive features having self-aligned edges
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US Patent 7214606 Method of fabricating a wire bond with multiple stitch bonds
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US Patent 7221050 Substrate having a functionally gradient coefficient of thermal expansion
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US Patent 7224058 Integrated circuit package employing a heat-spreader member
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US Patent 7229856 Method of manufacturing electronic part packaging structure
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US Patent 7230267 Organic semiconductor device
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US Patent 7233058 Memory card with an adaptor
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US Patent 7235455 Method of aligning an electron beam apparatus and semiconductor substrate utilizing an alignment mark
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US Patent 7238991 Semiconductor device with improved protection from electrostatic discharge
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US Patent 7239011 Memory card with a cap having indented portions
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US Patent 7242089 Miniature silicon condenser microphone
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US Patent 7247519 Method for making a semiconductor multi-package module having inverted bump chip carrier second package
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US Patent 7247889 III-nitride material structures including silicon substrates
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US Patent 7247931 Semiconductor package and leadframe therefor having angled corners
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US Patent 7253506 Micro lead frame package
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US Patent 7253511 Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
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US Patent 7259467 Semiconductor integrated circuit device
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US Patent 7262497 Bumpless assembly package
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US Patent 7262511 Conductive adhesive agent with ultrafine particles
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US Patent 7264980 Method of mounting light emitting element
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US Patent 7265038 Method for forming a multi-layer seed layer for improved Cu ECP
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US Patent 7265382 Method and apparatus employing integrated metrology for improved dielectric etch efficiency
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US Patent 7268392 Trench gate semiconductor device with a reduction in switching loss
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US Patent 7271033 Method for fabricating chip package
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US Patent 7271471 Metal substrate apparatus, method of manufacturing an IC card module apparatus, and an IC card module apparatus
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US Patent 7271475 Memory card with connecting portions for connection to an adapter
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US Patent 7274099 Method of embedding semiconductor chip in support plate
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US Patent 7276399 Method of designing a module-based flip chip substrate design
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US Patent 7276791 Board having alternating rows of processors and memories
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US Patent 7279361 Method for making a semiconductor multi-package module having wire bond interconnect between stacked packages
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US Patent 7279366 Method for assembling semiconductor die packages with standard ball grid array footprint
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US Patent 7279771 Wiring board mounting a capacitor
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US Patent 7279780 Quad flat no-lead (QFN) grid array package, method of making and memory module and computer system including same
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US Patent 7282390 Stacked die-in-die BGA package with die having a recess
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US Patent 7282392 Method of fabricating a stacked die in die BGA package
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US Patent 7285847 Chip stack package, connecting board, and method of connecting chips
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US Patent 7288434 Method for making semiconductor multi-package module having inverted second package and including additional die or package stacked on second package
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US Patent 7294565 Method of fabricating a wire bond pad with Ni/Au metallization
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US Patent 7294918 Memory card with connecting portions for connection to an adapter
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US Patent 7294921 System-on-a-chip with multi-layered metallized through-hole interconnection
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US Patent 7294926 Chip cooling system
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US Patent 7297563 Method of making contact pin card system
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US Patent 7297614 Method for fabricating circuitry component
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US Patent 7300850 Method of forming a self-aligned transistor
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US Patent 7306973 Method for making a semiconductor multipackage module including a processor and memory package assemblies
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US Patent 7307339 Semiconductor device having curved leads offset from the center of bonding pads
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US Patent 7309623 Method of fabricating a stacked die in die BGA package
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US Patent 7312525 Thermally enhanced package for an integrated circuit
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US Patent 7316935 Reticle for layout modification of wafer test structure areas
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US Patent 7317214 Amplifying solid-state image pickup device
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US Patent 7317243 Encapsulated lead having step configuration
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US Patent 7319055 Method of fabricating a semiconductor device utilizing crystallization of semiconductor region with laser beam
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US Patent 7326630 Method of fabricating semiconductor device utilizing laser irradiation
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US Patent 7329932 Microelectromechanical (MEM) viscosity sensor and method
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US Patent 7332376 Method of encapsulating packaged microelectronic devices with a barrier
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US Patent 7332757 MOSFET package
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US Patent 7332812 Memory card with connecting portions for connection to an adapter
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US Patent 7332816 Method of fabricating crossing wiring pattern on a printed circuit board
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US Patent 7342267 MOSFET package
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US Patent 7342301 Connection device with actuating element for changing a conductive state of a via
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US Patent 7348678 Integrated circuit package to provide high-bandwidth communication among multiple dice
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US Patent 7351610 Method of fabricating a semiconductor multi-package module having a second package substrate with an exposed metal layer wire bonded to a first package substrate
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US Patent 7351994 Noble high-k device
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US Patent 7354799 Methods for anchoring a seal ring to a substrate using vias and assemblies including an anchored seal ring
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US Patent 7354800 Method of fabricating a stacked integrated circuit package system
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US Patent 7355278 Mold die for a semiconductor device
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US Patent 7355283 Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging
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US Patent 7358115 Method of fabricating a semiconductor assembly including chip scale package and second substrate with exposed substrate surfaces on upper and lower sides
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US Patent 7358605 Heat dissipation structure for electronic device
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US Patent 7361944 Electrical device with a plurality of thin-film device layers
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US Patent 7361990 Reducing cracking of high-lead or lead-free bumps by matching sizes of contact pads and bump pads
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US Patent 7364945 Method of mounting an integrated circuit package in an encapsulant cavity
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US Patent 7364946 Method of fabricating a semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package
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US Patent 7368319 Stacked integrated circuit package-in-package system
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US Patent 7371608 Method of fabricating a stacked die having a recess in a die BGA package
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US Patent 7371612 Method of fabrication of stacked semiconductor devices
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US Patent 7372141 Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides
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US Patent 7372143 Printed circuit board including via contributing to superior characteristic impedance
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US Patent 7372145 Bonded assembly having improved adhesive bond strength
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US Patent 7375432 Via attached to a bond pad utilizing a tapered interconnect
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US Patent 7378297 Methods of bonding two semiconductor devices
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US Patent 7381589 Silicon condenser microphone and manufacturing method
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US Patent 7381995 Lighting device with flipped side-structure of LEDs
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US Patent 7382005 Circuit component with bump formed over chip
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US Patent 7382042 COF flexible printed wiring board and method of producing the wiring board
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US Patent 7382048 Acoustic transducer module
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US Patent 7384809 Method of forming three-dimensional features on light emitting diodes for improved light extraction
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US Patent 7391101 Semiconductor pressure sensor
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US Patent 7394125 Recessed channel with separated ONO memory device
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US Patent 7394146 MOSFET package
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US Patent 7394148 Module having stacked chip scale semiconductor packages
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US Patent 7397070 Self-aligned transistor
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US Patent 7397117 Chip package with die and substrate
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US Patent 7399661 Method for making an integrated circuit substrate having embedded back-side access conductors and vias
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US Patent 7400002 MOSFET package
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US Patent 7405109 Method of fabricating the routing of electrical signals
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US Patent 7405143 Method for fabricating a seed layer
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US Patent 7405159 Method of fabricating a semiconductor device package having a semiconductor element with a roughened surface
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US Patent 7405448 Semiconductor device having a resistance for equalizing the current distribution
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US Patent 7405467 Power module package structure
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US Patent 7408241 Semiconductor device with a recessed bond pad
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US Patent 7414309 Encapsulated electronic part packaging structure
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US Patent 7414312 Memory-module board layout for use with memory chips of different data widths
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US Patent 7414317 BGA package with concave shaped bonding pads
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US Patent 7416993 Patterned nanowire articles on a substrate and methods of making the same
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US Patent 7417299 Direct connection multi-chip semiconductor element structure
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US Patent 7419912 Laser patterning of light emitting devices
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US Patent 7423341 Plastic overmolded packages with mechanically decoupled lid attach attachment
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US Patent 7425465 Method of fabricating a multi-post structures on a substrate
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US Patent 7425470 Microelectronic component assemblies employing lead frames having reduced-thickness inner lengths
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US Patent 7425473 Method of fabricating a thin film transistor for an array panel
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US Patent 7425756 Semiconductor device and electronic device
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US Patent 7429761 High power diode utilizing secondary emission
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US Patent 7429786 Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides
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US Patent 7429787 Semiconductor assembly including chip scale package and second substrate with exposed surfaces on upper and lower sides
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US Patent 7432580 Semiconductor device with a substrate having a spiral shaped coil
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US Patent 7435619 Method of fabricating a 3-D package stacking system
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US Patent 7436057 Elastomer interposer with voids in a compressive loading system
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US Patent 7439083 Technique for compensating for substrate shrinkage during manufacture of an electronic assembly
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US Patent 7439547 Micro electro mechanical system apparatus
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US Patent 7439616 Miniature silicon condenser microphone
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US Patent 7443023 High capacity thin module system
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US Patent 7446410 Circuit module with thermal casing systems
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US Patent 7449370 Production process for manufacturing such semiconductor package
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US Patent 7459784 High capacity thin module system
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US Patent 7465610 Method for operating an H-bridge drive utilizing a pair of high and low side MOSFETS
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US Patent 7466022 Wafer-level seal for non-silicon-based devices
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US Patent 7470981 Semiconductor device with varying dummy via-hole plug density
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US Patent 7473943 Gate configuration for nanowire electronic devices
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US Patent 7476564 Flip-chip packaging process using copper pillar as bump structure
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US Patent 7482259 Chip structure and process for forming the same
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US Patent 7482684 Semiconductor device with a dopant region in a lower wire
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US Patent 7494847 Method for making a semiconductor multi-package module having inverted wire bond carrier second package
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US Patent 7495323 Semiconductor package structure having multiple heat dissipation paths and method of manufacture
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US Patent 7501295 Method of fabricating a reflective electrode for a semiconductor light emitting device
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US Patent 7501703 Acoustic transducer module
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US Patent 7504719 Printed wiring board having a roughened surface formed on a metal layer, and method for producing the same
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US Patent 7508006 Circuit board structure of integrated optoelectronic component
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US Patent 11189542 Method for fabricating an electronic module via compression molding
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US Patent 11189544 Plurality of cooling tubes with coolant for a power conversion package
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US Patent 7518237 Microfeature systems including adhered microfeature workpieces and support members
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US Patent 7518241 Wafer structure with a multi-layer barrier in an UBM layer network device with power supply
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US Patent 7521788 Semiconductor module with conductive element between chip packages
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US Patent 7524737 Method of fabricating a semiconductor chip with a nitride compound semiconductor material
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US Patent 7525190 Printed wiring board with wiring pattern having narrow width portion
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US Patent 7531849 High performance FET devices
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US Patent 7534635 Getter precursors for hermetically sealed packaging
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US Patent 7535056 Semiconductor device having a low concentration layer formed outside a drift layer
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US Patent 7535095 Printed wiring board and method for producing the same
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US Patent 7537962 Method of fabricating a shielded stacked integrated circuit package system
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US Patent 7537964 Method of fabricating a miniature silicon condenser microphone
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US Patent 7538390 Semiconductor device with PMOS and NMOS transistors
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US Patent 7538413 Semiconductor components having through interconnects
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US Patent 7538422 Integrated circuit micro-cooler having multi-layers of tubes of a CNT array
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US Patent 7538441 Chip with power and signal pads connected to power and signal lines on substrate
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US Patent 7541222 Wire sweep resistant semiconductor package and manufacturing method therefor
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US Patent 7545029 Stack microelectronic assemblies
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US Patent 7547581 Manufacturing method of a semiconductor device to suppress generation of whiskers
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US Patent 7547582 Method of fabricating a surface adapting cap with integral adapting material for single and multi chip assemblies
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US Patent 7547962 Chip package with a ring having a buffer groove that surrounds the active region of a chip
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US Patent 7547974 Wiring substrate with improvement in tensile strength of traces
‌
US Patent 7550321 Substrate having a functionally gradient coefficient of thermal expansion
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US Patent 7550832 Stackable semiconductor package
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US Patent 7550846 Conductive bump with a plurality of contact elements
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US Patent 7553696 Method for implementing component placement suspended within grid array packages for enhanced electrical performance
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US Patent 7553699 Method of fabricating microelectronic devices
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US Patent 7553703 Methods of forming an interconnect structure
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US Patent 7553728 Method of fabricating a non-volatile semiconductor memory
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US Patent 7554176 Integrated circuits having a multi-layer structure with a seal ring
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US Patent 7554177 Attachment system incorporating a recess in a structure
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US Patent 7556987 Method of fabricating an integrated circuit with etched ring and die paddle
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US Patent 7560744 Package optical chip with conductive pillars
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US Patent 7563647 Integrated circuit package system with interconnect support
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US Patent 7563651 Method of fabricating a substrate with a concave surface
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US Patent 7566957 Support device with discrete getter material microelectronic devices
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US Patent 7569409 Isolation structures for CMOS image sensor chip scale packages
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US Patent 7573131 Die-up integrated circuit package with grounded stiffener
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US Patent 7575953 Stacked die with a recess in a die BGA package
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US Patent 7579687 Circuit module turbulence enhancement systems and methods
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US Patent 7579693 Mounting structure of ball grid array
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US Patent 7582556 Circuitry component and method for forming the same
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US Patent 7582968 Wiring board with a protective film greater in heights than bumps
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US Patent 7586194 Semiconductor device having exposed heat dissipating metal plate
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US Patent 7589409 Stacked packages and microelectronic assemblies incorporating the same
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US Patent 7598126 Use of nanoscale particles for creating scratch-resistant protective layers on semiconductor chips
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US Patent 7598604 Low profile semiconductor package
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US Patent 7598613 Flip chip bonding structure
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US Patent 7602072 Substrate having alignment marks and method of obtaining alignment information using the same
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US Patent 7608911 Semiconductor device package having a semiconductor element with a roughened surface
‌
US Patent 7608925 Relay board with bonding pads connected by wirings
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US Patent 7612384 Reflective electrode for a semiconductor light emitting apparatus
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US Patent 7612436 Packaged microelectronic devices with a lead frame
‌
US Patent 7612446 Structures to enhance cooling of computer memory modules
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US Patent 7622329 Method for fabricating core substrate using paste bumps
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US Patent 7626259 Heat sink for a high capacity thin module system
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US Patent 7626270 Coreless package substrate with conductive structures
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US Patent 7629239 Method of fabricating a semiconductor device with a dopant region in a lower wire
‌
US Patent 7629671 Semiconductor device having a resin protrusion with a depression and method manufacturing the same
‌
US Patent 7629677 Semiconductor package with inner leads exposed from an encapsulant
‌
US Patent 7629682 Wafer level package configured to compensate size difference in different types of packages
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US Patent 7632717 Plastic overmolded packages with mechancially decoupled lid attach attachment
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US Patent 7633156 Acoustic transducer module
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US Patent 7633157 Microelectronic devices having a curved surface and methods for manufacturing the same
‌
US Patent 7636234 Apparatus configurations for affecting movement of fluids within a microelectric topography processing chamber
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US Patent 7638419 Method of fabricating a via attached to a bond pad utilizing a tapered interconnect
‌
US Patent 7638813 Methods of fabrication for flip-chip image sensor packages
‌
US Patent 7638870 Packaging for high speed integrated circuits
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US Patent 7642158 Semiconductor memory device and method of production
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US Patent 7645634 Method of fabricating module having stacked chip scale semiconductor packages
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US Patent 7646077 Methods and structure for forming copper barrier layers integral with semiconductor substrates structures
‌
US Patent 7648869 Method of fabricating semiconductor structures for latch-up suppression
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US Patent 7652347 Semiconductor package having embedded passive elements and method for manufacturing the same
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US Patent 7652364 Crossing conductive traces in a PCB
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US Patent 7671466 Semiconductor package having heat dissipating device with cooling fluid
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US Patent 7675161 Semiconductor device with wirings having varying lengths
‌
US Patent 7678619 Method of manufacturing a thin film transistor matrix substrate
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US Patent 7679180 Bond pad design to minimize dielectric cracking
‌
US Patent 7687313 Method of fabricating a semiconductor multi package module having an inverted package stacked over ball grid array (BGA) package
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US Patent 7687315 Stacked integrated circuit package system and method of manufacture therefor
‌
US Patent 7687892 Quad flat package
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US Patent 7687904 Plurality of devices attached by solder bumps
‌
US Patent 7691680 Method of fabricating microelectronic component assemblies employing lead frames having reduced-thickness inner lengths
‌
US Patent 7692279 Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
‌
US Patent 7696102 Methods for fabrication of three-dimensional structures
‌
US Patent 7700944 Semiconductor wafer, semiconductor chip, and semiconductor chip inspection method
‌
US Patent 7701014 Gating configurations and improved contacts in nanowire-based electronic devices
‌
US Patent 7709296 Coupling metal clad fiber optics for enhanced heat dissipation
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US Patent 7714329 Semiconductor device having thin film transistor
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US Patent 7719100 Power semiconductor module with MOS chip
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US Patent 7728423 Semiconductor device having step-wise connection structures for thin film elements
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US Patent 7732926 Semiconductor device having a through electrode with a low resistance and method of manufacturing the same
‌
US Patent 7737547 Dummy buried contacts and vias for improving contact via resistance in a semiconductor device
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US Patent 7737549 Circuit module with thermal casing systems
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US Patent 7737552 Device having a bonding structure for two elements
‌
US Patent 7741154 Integrated circuit package system with stacking module
‌
US Patent 7741158 Method of making thermally enhanced substrate-base package
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US Patent 7741652 Alignment device and application thereof
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US Patent 7745923 Cover substrate attached to a rim substrate with electrically connected through hole
‌
US Patent 7749807 Method of fabricating a semiconductor multipackage module including a processor and memory package assemblies
‌
US Patent 7750469 Insulating layer between bumps of semiconductor chip, and display panel using the same with anisotropic conductive film between semiconductor chip and substrate
‌
US Patent 7754531 Method for packaging microelectronic devices
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US Patent 7754558 Method of avoiding unwanted metal deposition on a semiconductor resistor structure
‌
US Patent 7755175 Multi-stack chip package with wired bonded chips
‌
US Patent 7759165 Nanospring
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US Patent 7759170 Fabrication method of semiconductor package having heat dissipation device
‌
US Patent 7759805 Semiconductor device encapsulated by an electrically conductive plastic housing composition with conductive particles
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US Patent 7763968 Semiconductor device featuring large reinforcing elements in pad area
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US Patent 7763969 Structure with semiconductor chips embeded therein
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US Patent 7768039 Field effect transistors with different gate widths
‌
US Patent 7772689 Semiconductor package with a conductive post and wiring pattern
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US Patent 7777309 Amplifier chip mounted on a lead frame
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US Patent 7786572 System in package (SIP) structure
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US Patent 7786573 Packaging chip having interconnection electrodes directly connected to plural wafers
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US Patent 7790544 Method of fabricating different gate oxides for different transistors in an integrated circuit
‌
US Patent 7791187 Semiconductor device
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US Patent 7791205 Interposers for semiconductor die packages with standard ball grill array footprint
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US Patent 7795723 Capped sensor
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US Patent 7799610 Method of fabricating a stacked die having a recess in a die BGA package
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US Patent 7799614 Method of fabricating a power electronic device
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US Patent 7800214 Semiconductor device
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US Patent 7807565 Method of forming bit line of flash memory device
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US Patent 7808075 Integrated circuit devices with ESD and I/O protection
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US Patent 7808091 Wafer structure with discrete gettering material
‌
US Patent 7811855 Method for producing a matrix for detecting electromagnetic radiation and method for replacing an elementary module of such a detection matrix
‌
US Patent 7812432 Chip package with a dam structure on a die pad
‌
US Patent 7820486 Method of fabricating a semiconductor device having a heat sink with an exposed surface
‌
US Patent 7821115 Tape carrier package including a heat dissipation element
‌
US Patent 7821122 Method and system for increasing circuitry interconnection and component capacity in a multi-component package
‌
US Patent 7821123 LED array cooling system
‌
US Patent 7821128 Power semiconductor device having lines within a housing
‌
US Patent 7821129 Low cost hermetic ceramic microcircuit package
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US Patent 7825512 Electronic package with compliant electrically-conductive ball interconnect
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US Patent 7829364 Method of fabricating a suspension microstructure
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US Patent 7829382 Method for making semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
‌
US Patent 7829385 Taped semiconductor device and method of manufacture
‌
US Patent 7829906 Three dimensional features on light emitting diodes for improved light extraction
‌
US Patent 7833810 Method of fabricating isolation structures for CMOS image sensor chip scale packages
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US Patent 7833832 Method of fabricating semiconductor components with through interconnects
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US Patent 7833840 Integrated circuit package system with down-set die pad and method of manufacture thereof
‌
US Patent 7838322 Method of enhancing an etch system
‌
US Patent 7842550 Method of fabricating quad flat non-leaded package
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US Patent 7847301 Electronic microcircuit having internal light enhancement
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US Patent 7847393 Conductive connecting pins for a package substrate
‌
US Patent 7851903 Infrared detector with plurality of metallization between first and second container members
‌
US Patent 7855100 Integrated circuit package system with an encapsulant cavity and method of fabrication thereof
‌
US Patent 7855438 Deep via construction for a semiconductor device
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US Patent 7859106 Multilayer printed circuit board using paste bumps
‌
US Patent 7863062 Semiconductor device with a shielding section to prevent condensation and optical device module having the semiconductor device
‌
US Patent 7863100 Integrated circuit packaging system with layered packaging and method of manufacture thereof
‌
US Patent 7863108 Integrated circuit packaging system with etched ring and die paddle and method of manufacture thereof
‌
US Patent 7863109 Integrated circuit packaging system with a protrusion on an inner stacking module and method of manufacture thereof
‌
US Patent 7863719 Wafer level chip scale package
‌
US Patent 7867876 Method of thinning a semiconductor substrate
‌
US Patent 7871857 Methods of forming multi-chip semiconductor substrates
‌
US Patent 7871870 Method of fabricating gate configurations for an improved contacts in nanowire based electronic devices
‌
US Patent 7871878 Method of fabricating PMOS and NMOS transistor on the same substrate
‌
US Patent 7875886 Semiconductor device having a thin film transistor
‌
US Patent 7883947 Method of fabricating a device with ESD and I/O protection
‌
US Patent 7884033 Method of depositing fluids within a microelectric topography processing chamber
‌
US Patent 7884373 Gallium nitride layer with diamond layers
‌
US Patent 7884403 Magnetic tunnel junction device and memory device including the same
‌
US Patent 7888171 Fabricating a gallium nitride layer with diamond layers
‌
US Patent 7888188 Method of fabicating a microelectronic die having a curved surface
‌
US Patent 7888788 Semiconductor device with reduced cross talk
‌
US Patent 7888789 Transfer material used for producing a wiring substrate
‌
US Patent 7888796 Controller chip mounted on a memory chip with re-wiring lines
‌
US Patent 7897433 Semiconductor chip with reinforcement layer and method of making the same
‌
US Patent 7901996 Integrated circuit package system with interconnection support and method of manufacture thereof
‌
US Patent 7902658 Integrated circuit having wide power lines
‌
US Patent 7902659 Conductive connecting pin and package substrate
‌
US Patent 7906843 Substrate having a functionally gradient coefficient of thermal expansion
‌
US Patent 7910385 Method of fabricating microelectronic devices
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US Patent 7915158 Method for forming an on-chip high frequency electro-static discharge device
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US Patent 7919852 Semiconductor device and insulating substrate utilizing a second conductor with a non-joint area
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US Patent 7927941 Method of fabricating field effect transistors with different gate widths
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US Patent 7928553 Power electronic device
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US Patent 7932614 Method of thinning a semiconductor substrate
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US Patent 7935612 Layer transfer using boron-doped SiGe layer
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US Patent 7936029 Hall effect element having a hall plate with a perimeter having indented regions
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US Patent 7943956 Semiconductor device comprising a housing containing a triggering unit
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US Patent 7943969 Transistor with a plurality of layers with different Ge concentrations
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US Patent 7947978 Semiconductor chip with bond area
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US Patent 7948082 Method of fabricating a patterned nanoscopic article
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US Patent 7948090 Capillary-flow underfill compositions, packages containing same, and systems containing same
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US Patent 7952188 Semiconductor module with a dielectric layer including a fluorocarbon compound on a chip
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US Patent 7952195 Stacked packages with bridging traces
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US Patent 7955903 Method of suppressing overflowing of an encapsulation resin in a semiconductor module
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US Patent 7956438 Integrated capacitor with interlinked lateral fins
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US Patent 7956458 Metal clad fiber optics for enhanced heat dissipation
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US Patent 7964947 Stacking packages with alignment elements
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US Patent 7964960 Semiconductor device having non parallel cleavage planes in a substrate and supporting substrate
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US Patent 7968372 Method of joining chips utilizing copper pillar
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US Patent 7968914 Multi-component electrical module
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US Patent 7972968 High density plasma gapfill deposition-etch-deposition process etchant
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US Patent 7977763 Chip package with die and substrate
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US Patent 7985620 Method of fabricating via first plus via last IC interconnect
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US Patent 7985991 MOSFET package
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US Patent 7989826 Semiconductor light emitting device
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US Patent 7989945 Spring connector for making electrical contact at semiconductor scales
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US Patent 7998758 Method of fabricating a magnetic stack design with decreased substrate stress
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US Patent 8003445 Integrated circuit packaging system with z-interconnects having traces and method of manufacture thereof
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US Patent 8003494 Method for producing a bonded wafer
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US Patent 8003984 Reticle for wafer test structure areas
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US Patent 8008127 Method of fabricating an integrated circuit having a multi-layer structure with a seal ring
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US Patent 8008143 Method to form a semiconductor device having gate dielectric layers of varying thicknesses
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US Patent 8012798 Method of fabricating stacked semiconductor chips
Edits on 13 Dec, 2021
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edited on 13 Dec, 2021
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US Patent 8012798 Method of fabricating stacked semiconductor chips
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edited on 8 Dec, 2021
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edited on 8 Dec, 2021
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Patent primary examiner of
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US Patent 8003984 Reticle for wafer test structure areas
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edited on 8 Dec, 2021
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Infobox
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US Patent 8003494 Method for producing a bonded wafer
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edited on 8 Dec, 2021
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edited on 8 Dec, 2021
Edits made to:
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Patent primary examiner of
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US Patent 7998758 Method of fabricating a magnetic stack design with decreased substrate stress
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edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7989945 Spring connector for making electrical contact at semiconductor scales
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edited on 8 Dec, 2021
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Infobox
Patent primary examiner of
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US Patent 7989826 Semiconductor light emitting device
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edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7985991 MOSFET package
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edited on 8 Dec, 2021
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Infobox
Patent primary examiner of
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US Patent 7985620 Method of fabricating via first plus via last IC interconnect
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edited on 8 Dec, 2021
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Infobox
Patent primary examiner of
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US Patent 7977763 Chip package with die and substrate
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edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7972968 High density plasma gapfill deposition-etch-deposition process etchant
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7968914 Multi-component electrical module
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edited on 8 Dec, 2021
Edits made to:
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Infobox
Patent primary examiner of
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US Patent 7968372 Method of joining chips utilizing copper pillar
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edited on 8 Dec, 2021
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edited on 8 Dec, 2021
Edits made to:
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Patent primary examiner of
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US Patent 7964947 Stacking packages with alignment elements
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edited on 7 Dec, 2021
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Patent primary examiner of
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US Patent 7956458 Metal clad fiber optics for enhanced heat dissipation
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edited on 7 Dec, 2021
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Patent primary examiner of
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US Patent 7956438 Integrated capacitor with interlinked lateral fins

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