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Aimee J. Li

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US Patent 7315934 Data processor and program for processing a data matrix
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US Patent 7320065 Multithread embedded processor with input/output capability
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US Patent 7343471 Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions
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US Patent 7343476 Intelligent SMT thread hang detect taking into account shared resource contention/blocking
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US Patent 7350056 Method and apparatus for issuing instructions from an issue queue in an information handling system
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US Patent 7353368 Method and apparatus for achieving architectural correctness in a multi-mode processor providing floating-point support
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US Patent 7366876 Efficient emulation instruction dispatch based on instruction width
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US Patent 7366877 Speculative instruction issue in a simultaneously multithreaded processor
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US Patent 7366880 Facilitating value prediction to support speculative program execution
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US Patent 7366884 Context switching system for a multi-thread execution pipeline loop and method of operation thereof
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US Patent 7380108 Automatic and transparent hardware conversion of traditional control flow to predicates
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US Patent 7395418 Using a transactional execution mechanism to free up processor resources used by a busy-waiting thread
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US Patent 7398374 Multi-cluster processor for processing instructions of one or more instruction threads
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US Patent 7404070 Branch prediction combining static and dynamic prediction techniques
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US Patent 7409530 Method and apparatus for compressing VLIW instruction and sharing subinstructions
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US Patent 7409534 Automatic and transparent hardware conversion of traditional control flow to predicates
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US Patent 7424596 Code interpretation using stack state information
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US Patent 7428630 Processor adapted to receive different instruction sets
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US Patent 7434036 System and method for executing software program instructions using a condition specified within a conditional execution instruction
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US Patent 7441106 Distributed processing in a multiple processing unit environment
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US Patent 7461238 Simple load and store disambiguation and scheduling at predecode
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US Patent 7467287 Method and apparatus for vector table look-up
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US Patent 7472259 Multi-cycle instructions
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US Patent 7478224 Microprocessor access of operand stack as a register file using native instructions
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US Patent 7480787 Method and structure for pipelining of SIMD conditional moves
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US Patent 7480788 Command time-out managing apparatus
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US Patent 7487333 High-performance, superscalar-based computer system with out-of-order instruction execution
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US Patent 7487340 Local and global branch prediction information storage
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US Patent 7493468 Method for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing
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US Patent 7496734 System and method for handling register dependency in a stack-based pipelined processor
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US Patent 7502913 Switch prefetch in a multicore computer chip
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US Patent 7502915 System and method using embedded microprocessor as a node in an adaptable computing machine
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US Patent 7509483 Methods and apparatus for meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors
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US Patent 7516310 Method to reduce the number of times in-flight loads are searched by store instructions in a multi-threaded processor
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US Patent 7516312 Presbyopic branch target prefetch method and apparatus
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US Patent 7526637 Adaptive execution method for multithreaded processor-based parallel system
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US Patent 7529916 Data processing apparatus and method for controlling access to registers
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US Patent 7536533 MCU based motor controller with pre-load register and DMA controller
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US Patent 7539849 Maintaining a double-ended queue in a contiguous array with concurrent non-blocking insert and remove operations using a double compare-and-swap primitive
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US Patent 7552313 VLIW digital signal processor for achieving improved binary translation
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US Patent 7558947 Method and apparatus for computing vector absolute differences
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US Patent 7577827 Data processor with multi-command instruction words
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US Patent 7581084 Method and apparatus for efficient loading and storing of vectors
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US Patent 7590826 Speculative data value usage
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US Patent 7596683 Switching processor threads during long latencies
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US Patent 7600096 Coprocessor extension architecture built using a novel split-instruction transaction model
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US Patent 7600104 Method and system for parallel vector data processing of vector data having a number of data elements including a defined first bit-length
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US Patent 7610472 Performing variable and/or bitwise shift operation for a shift instruction that does not provide a variable or bitwise shift option
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US Patent 7610473 Apparatus, method, and instruction for initiation of concurrent instruction streams in a multithreading microprocessor
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US Patent 7613912 System and method for simulating hardware interrupts
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US Patent 7624252 Processing device, method of determining internal configuration of processing device, and processing system
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US Patent 7627737 Processing element and method connecting registers to processing logic in a plurality of configurations
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US Patent 7634640 Data processing apparatus having program counter sensor
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US Patent 7640418 Dynamic field patchable microarchitecture
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US Patent 7647478 Suppression of store checking
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US Patent 7647479 Non-temporal memory reference control mechanism
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US Patent 7650483 Execution of instructions within a data processing apparatus having a plurality of processing units
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US Patent 7660970 Register allocation method and system for program compiling
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US Patent 7664934 Data processor decoding instruction formats using operand data
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US Patent 7664937 Self-checking code for tamper-resistance based on code overlapping
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US Patent 7673117 Operation apparatus
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US Patent 7673118 System and method for vector-parallel multiprocessor communication
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US Patent 7676647 System and method of processing data using scalar/vector instructions
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US Patent 7676649 Computing machine with redundancy and related systems and methods
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US Patent 7676654 Extended register space apparatus and methods for processors
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US Patent 7681018 Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
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US Patent 7689812 Method and system for restoring register mapper states for an out-of-order microprocessor
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US Patent 7694111 Processor employing loadable configuration parameters to reduce or eliminate setup and pipeline delays in a pipeline system
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US Patent 7698535 Asynchronous multiple-order issue system architecture
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US Patent 7698542 Circuit and method for comparing program counter values
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US Patent 7702888 Branch predictor directed prefetch
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US Patent 7707389 Multi-ISA instruction fetch unit for a processor, and applications thereof
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US Patent 7707395 Data processing system with trace co-processor
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US Patent 7711928 Method and structure for explicit software control using scoreboard status information
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US Patent 7711930 Apparatus and method for decreasing the latency between instruction cache and a pipeline processor
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US Patent 7711932 Scalable rename map table recovery
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US Patent 7716460 Effective use of a BHT in processor having variable length instruction set execution modes
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US Patent 7721070 High-performance, superscalar-based computer system with out-of-order instruction execution
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US Patent 7725678 Method and apparatus for producing an index vector for use in performing a vector permute operation
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US Patent 7725684 Speculative instruction issue in a simultaneously multithreaded processor
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US Patent 7725685 Intelligent SMT thread hang detect taking into account shared resource contention/blocking
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US Patent 7725686 Systems and methods for processing buffer data retirement conditions
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US Patent 7725689 Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts
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US Patent 7725695 Branch prediction apparatus for repurposing a branch to instruction set as a non-predicted branch
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US Patent 7725696 Method and apparatus for modulo scheduled loop execution in a processor architecture
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US Patent 7725699 Data byte insertion circuitry
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US Patent 7730283 Simple load and store disambiguation and scheduling at predecode
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US Patent 7730284 Pipelined instruction processor with data bypassing and disabling circuit
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US Patent 7730286 Software assisted nested hardware transactions
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US Patent 7734899 Reducing data hazards in pipelined processors to provide high processor utilization
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US Patent 7739482 High-performance, superscalar-based computer system with out-of-order instruction execution
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US Patent 7743231 Fast sparse list walker
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US Patent 7743235 Processor having a dedicated hash unit integrated within
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US Patent 7747844 Acquiring instruction addresses associated with performance monitoring events
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US Patent 7752419 Method and system for managing hardware resources to implement system functions using an adaptive computing architecture
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US Patent 7757065 Instruction segment recording scheme
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US Patent 7757066 System and method for executing variable latency load operations in a date processor
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US Patent 7757070 Methods, apparatuses, and system for facilitating control of multiple instruction threads
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US Patent 7765386 Scalable parallel pipeline floating-point unit for vector processing
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US Patent 7765388 Interrupt verification support mechanism
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US Patent 7769980 Parallel operation device allowing efficient parallel operational processing
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US Patent 7774581 Apparatus for compressing instruction word for parallel processing VLIW computer and method for the same
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US Patent 7774585 Interrupt and trap handling in an embedded multi-thread processor to avoid priority inversion and maintain real-time operation
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US Patent 7779237 Adaptive execution frequency control method for enhanced instruction throughput
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US Patent 7783862 Method and apparatus for an inductive doubling architecture
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US Patent 7783868 Instruction fetch control device and method thereof with dynamic configuration of instruction buffers
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US Patent 7783870 Branch target address cache
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US Patent 7793072 Vector execution unit to process a vector instruction by executing a first operation on a first set of operands and a second operation on a second set of operands
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US Patent 7793077 Alignment and ordering of vector elements for single instruction multiple data processing
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US Patent 7797514 Scalable multi-threaded sequencing/synchronizing processor architecture
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US Patent 7802079 Parallel data processing apparatus
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US Patent 7802080 Null exception handling
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US Patent 7805591 Method and system for dual-core processing
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US Patent 7805596 Highly integrated multiprocessor system
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US Patent 7818541 Data processing architectures
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US Patent 7818542 Method and apparatus for length decoding variable length instructions
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US Patent 7818543 Method and apparatus for length decoding and identifying boundaries of variable length instructions
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US Patent 7822955 Data processing apparatus and method for utilizing endianess independent data values
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US Patent 7827393 Branch prediction apparatus, its method and processor
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US Patent 7836276 System and method for processing thread groups in a SIMD architecture
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US Patent 7844797 System and method for handling load and/or store operations in a superscalar microprocessor
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US Patent 7844799 Method and system for pipeline reduction
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US Patent 7849290 Store queue architecture for a processor that supports speculative execution
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US Patent 7870372 Interrupt handling
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US Patent 7886131 Multithread processor with thread based throttling
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US Patent 7886133 Information processing apparatus and method for accelerating information processing
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US Patent 7890735 Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture
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US Patent 7904703 Method and apparatus for idling and waking threads by a multithread processor
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US Patent 7904704 Instruction dispatching method and apparatus
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US Patent 7925871 Identification and correction of cyclically recurring errors in one or more branch predictors
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US Patent 7930526 Compare and branch mechanism
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US Patent 7937558 Processing system with interspersed processors and communication elements
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US Patent 7937568 Adaptive execution cycle control method for enhanced instruction throughput
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US Patent 7937572 Run-time selection of feed-back connections in a multiple-instruction word processor
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US Patent 7941640 Secure processors having encoded instructions
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US Patent 7941654 Local and global branch prediction information storage
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US Patent 7949860 Multi thread processor having dynamic reconfiguration logic circuit
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US Patent 7966479 Concurrent vs. low power branch prediction
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US Patent 7979676 Method for instructing a data processor to process data
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US Patent 7979677 Adaptive allocation of reservation station entries to an instruction set with variable operands in a microprocessor
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US Patent 7987338 Processing system with interspersed processors using shared memory of communication elements
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US Patent 7987339 Processing system with interspersed processors and dynamic pathway creation
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US Patent 8006067 Flexible results pipeline for processing element
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US Patent 8006069 Inter-processor communication method
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US Patent 8006072 Reducing data hazards in pipelined processors to provide high processor utilization
Edits on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
Edits made to:
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Patent primary examiner of
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US Patent 8006072 Reducing data hazards in pipelined processors to provide high processor utilization
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Golden AI
edited on 8 Dec, 2021
Edits made to:
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Infobox
Patent primary examiner of
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US Patent 8006067 Flexible results pipeline for processing element
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Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
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US Patent 8006069 Inter-processor communication method
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Golden AI
edited on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
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US Patent 7987339 Processing system with interspersed processors and dynamic pathway creation
Edits on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7979676 Method for instructing a data processor to process data
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Golden AI
edited on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7966479 Concurrent vs. low power branch prediction
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Golden AI
edited on 7 Dec, 2021
Edits made to:
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Patent primary examiner of
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US Patent 7949860 Multi thread processor having dynamic reconfiguration logic circuit
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Golden AI
edited on 7 Dec, 2021
Edits made to:
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Patent primary examiner of
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US Patent 7941654 Local and global branch prediction information storage
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Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7941640 Secure processors having encoded instructions
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Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7937572 Run-time selection of feed-back connections in a multiple-instruction word processor
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Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7937568 Adaptive execution cycle control method for enhanced instruction throughput
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Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7937558 Processing system with interspersed processors and communication elements
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Golden AI
edited on 7 Dec, 2021
Edits made to:
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Patent primary examiner of
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US Patent 7930526 Compare and branch mechanism
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Golden AI
edited on 7 Dec, 2021
Edits on 7 Dec, 2021
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Golden AI
edited on 7 Dec, 2021
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Patent primary examiner of
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US Patent 7904704 Instruction dispatching method and apparatus

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