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A. M. Thompson

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Edits on 24 Aug, 2022
"Edit from table cell"
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Екатерина Петровская
edited on 24 Aug, 2022
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Twitter URL
https://twitter.com/AM_ThompsonEdu
Edits on 15 Dec, 2021
"Remove inverse infobox"
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Golden AI
edited on 15 Dec, 2021
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Patent primary examiner of
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US Patent 7089518 Method and program product for modelling behavior of asynchronous clocks in a system having multiple clocks
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US Patent 7089519 Method and system for performing placement on non Manhattan semiconductor integrated circuits
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US Patent 7093208 Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices
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US Patent 7093210 Method of manufacturing circuit device using a communication network
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US Patent 7093220 Method for generating constrained component placement for integrated circuits and packages
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US Patent 7096448 Method and apparatus for diagonal routing by using several sets of lines
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US Patent 7096449 Layouts with routes with different widths in different directions on the same layer, and method and apparatus for generating such layouts
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US Patent 7100137 Method and apparatus for quantifying the quality of placement configurations in a partitioned region of an integrated circuit layout
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US Patent 7103859 System and method for improving testability independent of architecture
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US Patent 7103860 Verification of embedded test structures in circuit designs
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US Patent 7107553 Method and apparatus for solving constraints
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US Patent 7107556 Method and system for implementing an analytical wirelength formulation for unavailability of routing directions
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US Patent 7107569 Design method and apparatus for a semiconductor integrated circuit comprising checkers verifying the interface between circuit blocks
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US Patent 7111269 Comparison of two hierarchical netlist to generate change orders for updating an integrated circuit layout
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US Patent 7114135 Routing of test signals of integrated circuits
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US Patent 7114141 Method and apparatus for decomposing a design layout
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US Patent 7117462 Circuit operation verifying method and apparatus
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US Patent 7117472 Placement of a clock signal supply network during design of integrated circuits
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US Patent 7131094 Method and system for automatically extracting data from a textual bump map
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US Patent 7131097 Logic generation for multiple memory functions
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US Patent 7131103 Conductor stack shifting
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US Patent 7131105 System and method for automatic mesh generation from a system-level MEMS design
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US Patent 7134102 Automated layout transformation system and method
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US Patent 7134105 Multiple level transistor abstraction for dynamic circuits
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US Patent 7134111 Layout method and apparatus for arrangement of a via offset from a center axis of a conductor and semiconductor device thereof
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US Patent 7137080 Method for determining and using leakage current sensitivities to optimize the design of an integrated circuit
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US Patent 7137085 Wafer level global bitmap characterization in integrated circuit technology development
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US Patent 7137095 Freeway routing system for a gate array
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US Patent 7139992 Short path search using tiles and piecewise linear cost propagation
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US Patent 7139995 Integration of a run-time parameterizable core with a static circuit design
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US Patent 7143375 Logical equivalence verifying device, method and computer readable medium thereof
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US Patent 7143387 Method, system and program product providing a configuration specification language that supports the definition of links between configuration constructs
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US Patent 7146596 Integrated circuit chip having a ringed wiring layer interposed between a contact layer and a wiring grid
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US Patent 7146598 Method and apparatus for configuring a programmable logic device
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US Patent 7155686 Placement and routing method to reduce Joule heating
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US Patent 7162703 Electrical design rule checking expert traverser system
Edits on 20 Nov, 2021
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Golden AI
edited on 20 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7162703 Electrical design rule checking expert traverser system
Edits on 19 Nov, 2021
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Golden AI
edited on 19 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7155686 Placement and routing method to reduce Joule heating
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Golden AI
edited on 19 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7146598 Method and apparatus for configuring a programmable logic device
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Golden AI
edited on 19 Nov, 2021
Golden AI profile picture
Golden AI
edited on 19 Nov, 2021
Golden AI profile picture
Golden AI
edited on 19 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7143375 Logical equivalence verifying device, method and computer readable medium thereof
Golden AI profile picture
Golden AI
edited on 19 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7139995 Integration of a run-time parameterizable core with a static circuit design
Golden AI profile picture
Golden AI
edited on 19 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7139992 Short path search using tiles and piecewise linear cost propagation
Golden AI profile picture
Golden AI
edited on 19 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7137095 Freeway routing system for a gate array
Golden AI profile picture
Golden AI
edited on 19 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7137085 Wafer level global bitmap characterization in integrated circuit technology development
Golden AI profile picture
Golden AI
edited on 19 Nov, 2021
Edits on 18 Nov, 2021
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Golden AI
edited on 18 Nov, 2021
Golden AI profile picture
Golden AI
edited on 18 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7134105 Multiple level transistor abstraction for dynamic circuits
Golden AI profile picture
Golden AI
edited on 18 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7134102 Automated layout transformation system and method
Golden AI profile picture
Golden AI
edited on 18 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7131105 System and method for automatic mesh generation from a system-level MEMS design
Golden AI profile picture
Golden AI
edited on 18 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7131103 Conductor stack shifting
Golden AI profile picture
Golden AI
edited on 18 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7131097 Logic generation for multiple memory functions
Golden AI profile picture
Golden AI
edited on 18 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7131094 Method and system for automatically extracting data from a textual bump map

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