Patent attributes
A jitter counter according to the present invention is connected to a PLL circuit for generating a clock signal, which is necessary for signal processing, from a binary signal, and counts jitters of the binary signal. The jitter counter comprises: a determination signal generation circuit which uses an output signal from a VCO constituting the PLL circuit and the like to generate a determination signal that has a given pulse width having the phase center at the position of a pulse edge of the clock signal; a phase determination circuit which at every time when logic inversion of the binary signal occurs, determines whether or not the inversion position is present in a determination section given by the pulse width of the determination signal based on an output signal from a phase comparator constituting the PLL circuit and on the determination signal; a phase counter which counts the number of times that inversion positions of the binary signal are not present in the determination section (or times that inversion positions of the binary signal are present in the determination section) based on an output signal from the phase determination circuit, wherein a count value of the phase counter is output as a jitter count value.
