US Patent 7843745 Delay locked operation in semiconductor memory device

A semiconductor memory device has a control circuit capable of properly controlling a delay locked loop in a variety of operational modes. The semiconductor memory device includes a clock buffer for externally receiving a system clock to output it as an internal clock, a delay locked loop unit for controlling a delay of the internal clock such that a data output timing is synchronized with the system clock; a data output buffer for synchronizing data with the delay locked internal clock, thereby outputting the data, and a clock buffer control unit, responsive to a previous operation state, for generating an enable signal controlling the on/off switching of the clock buffer.