US Patent 7692313 Substrate and semiconductor package for lessening warpage

A substrate with reduced substrate warpage and a semiconductor package utilizing the substrate are revealed. The substrate primarily comprises a core where a wiring layer and a first solder mask are formed on one surface of the core, and a second solder mask and a die-attaching layer are formed on the other surface of the core. The first solder mask has a thickness difference with respect to the second solder mask in a manner to reduce the warpage of the substrate caused by thermal stresses due to temperature differences can be well under control. Therefore, the manufacturing cost of the substrate can be lower without adding extra stiffeners to achieve substrate warpage control during semiconductor packaging processes.