US Patent 7663526 Analog-to-digital converter architecture and method with reduced non-linearity

An analog-to-digital converter circuit and method with reduced non-linearity are described. The circuit includes an amplifier module having at least one active input coupled to at least three capacitor devices. The circuit further includes multiple switches coupled to each respective capacitor device. One switch coupled to each capacitor device is further coupled to an output of the amplifier module, such that each capacitor device can be selectively coupled to the output of the amplifier module. At least one switch coupled to each capacitor device is further coupled to a reference voltage source to receive at least one reference voltage signal. Finally, at least one switch coupled to each capacitor device is further coupled to receive an input voltage signal.