Patent attributes
A semiconductor memory that reduces the power consumption of a memory cell array without exercising control by a microprocessor. The semiconductor memory comprises a memory cell array, a switch for turning on/off power corresponding to row addresses of the memory cell array, an address control section for exercising sequence control on the basis of a write pointer (WP) generated at the time of a write signal being inputted for designating a row address to which data of a predetermined data stream is to be written and a read pointer (RP) generated at the time of a read signal being inputted for designating a row address from which the data is to be read out, and a switch signal output section for generating switch signals for controlling the switch on the basis of the WP and the RP.
