US Patent 7529127 Memory device and method thereof

A memory device and method thereof are provided. The memory device may comprise a first buffer for receiving most significant bit (MSB) data and least significant bit (LSB) data to be stored within a memory cell; a second buffer for loading LSB data stored in the memory cell; and a data loader for generating at least one load signal based upon logic levels of the received MSB data in the first buffer and the loaded LSB data in the second buffer, the at least one load signal being configured to control programming permissions for the memory cell.