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US Patent 7452764 Gate-induced strain for MOS performance improvement

Patent 7452764 was granted and assigned to Intel on November, 2008 by the United States Patent and Trademark Office.

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Patent abstractTimelineTable: Further ResourcesReferences
Is a
Patent
Patent
1

Patent attributes

Current Assignee
Intel
Intel
1
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
1
Patent Number
74527641
Patent Inventor Names
Stephen M. Cea1
Thomas Hoffmann1
Martin D. Giles1
Date of Patent
November 18, 2008
1
Patent Application Number
110703651
Date Filed
March 1, 2005
1
Patent Primary Examiner
‌
Hoai V Pham
1
Patent abstract

A method including forming a device on a substrate, the device including a gate electrode on a surface of the substrate; a first junction region and a second junction region in the substrate adjacent the gate electrode; and depositing a straining layer on the gate electrode.

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