US Patent 7452764 Gate-induced strain for MOS performance improvement
Patent 7452764 was granted and assigned to Intel on November, 2008 by the United States Patent and Trademark Office.
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Patent Inventor Names
Martin D. Giles0
Stephen M. Cea0
Thomas Hoffmann0
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Article (+290 characters)
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Patent abstract
A method including forming a device on a substrate, the device including a gate electrode on a surface of the substrate; a first junction region and a second junction region in the substrate adjacent the gate electrode; and depositing a straining layer on the gate electrode.
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US Patent 07452764 Gate-induced strain for MOS performance improvement US Patent 7452764 Gate-induced strain for MOS performance improvement
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Patent Number
074527640
Patent Number
74527640
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Current Assignee
Patent Jurisdiction
Patent Number
074527640
Date of Patent
November 18, 2008
0Patent Application Number
110703650
Date Filed
March 1, 2005
0Official Website
Patent Primary Examiner
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US Patent 07452764 Gate-induced strain for MOS performance improvement
Infobox
Is a
Current assignee
Patent jurisdiction
Patent number
07452764
Date of patent
November 18, 2008
Patent application number
11070365
Date Filed
March 1, 2005
Patent primary examiner
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