Patent attributes
A logic analyzer having internal access to the test buses, clocks and events of a chip is used to debug the chip. The logic analyzer is designed with the capability to share existing memory in the chip during the debug process. Additionally, the configuration of the logic analyzer and observation of the acquired results in the shared memory can be accessed through normal control interfaces of the chip and does not require special test cards. The logic analyzer includes a clocking function, a trigger function, a signal multiplexer, and a memory block. The clocking function is configured to select as the sample clock for the function any of the clocks in the integrated circuit. In addition, the clocking function may provide a means to decimate these clocks by some factor to sample over larger intervals.
