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US Patent 7305635 Serial implementation of assertion checking logic circuit

Patent 7305635 was granted and assigned to DAFCA on December, 2007 by the United States Patent and Trademark Office.

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Patent
Patent

Patent attributes

Current Assignee
‌
DAFCA
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
7305635
Patent Inventor Names
Miron Abramovici7
Gerard Philippe Memmi7
Date of Patent
December 4, 2007
Patent Application Number
11051774
Date Filed
February 4, 2005
Patent Citations Received
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US Patent 11748457 Systems and methods for policy linking and/or loading for secure initialization
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US Patent 11875180 Systems and methods for stalling host processor
1
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US Patent 11841956 Systems and methods for data lifecycle protection
2
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US Patent 11977613 System and method for translating mapping policy into code
3
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US Patent 12124576 Systems and methods for policy violation processing
4
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US Patent 12124566 Systems and methods for metadata encoding
5
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US Patent 12079197 Systems and methods for updating metadata
6
Patent Primary Examiner
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Thuan Do
Patent abstract

Serial assertion checking is realized in a System On a Chip (SoC) device by connecting scan chain output to a bit extractor configured within a functionally reconfigurable module that is part of the SoC, which extracts the bits necessary for the assertion checking. The extracted bits are applied to a finite state machine that implements the assertion checking.

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