US Patent 7236015 Dynamic biasing circuit for continuous time comparators

A method for dynamically adapting the biasing current for a fast switching CMOS comparator is achieved. The difference of the two input signals of said comparator controls the comparator's biasing current, where the biasing current is high only when the difference is low and the comparator's switching is likely to happen and where the biasing current is kept low at other times. In a current mirroring circuit, the voltage difference at the comparator inputs controls the mirroring ratio. The biasing current reaches its maximum when the input voltage difference approaches zero. Once the input voltage difference crosses zero and continues to change in the same direction as before, that is after the polarity of the voltage difference changed, the control mechanism alternates the connection of the comparator input signals to the current controlling elements, in order to now reduce the current with a further increase of the voltage difference. The same circuit can have opposite characteristics, providing a minimum current when the input voltage difference is low, by reversing the connection of the inputs to the current controlling elements. An alternative circuit is described, that does not need said alternating mechanism.