US Patent 7181575 Instruction cache using single-ported memories

Systems, methodologies, media, and other embodiments associated with cache systems are described. One exemplary system embodiment includes an instruction cache comprising single-ported memories. The example system can further include a cache control logic configured to process cache events of different types that may be received by the instruction cache, and being configured with a multi-stage pipeline that coordinates processing of the cache events to the single-ported memories. The multi-stage pipeline can have different stages pre-assigned as read/write stages for the cache events to minimize access conflicts between the cache events.