US Patent 7167043 Decoupling circuit for co-packaged semiconductor devices
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A model for noise coupling in copackaged semiconductor devices due to coupling through parasitic impedances, and a method and decoupling circuit to minimize the effects of such noise. In one example, which is not intended to be limiting either as to the application of the invention or its implementation, a decoupling circuit for a power factor correction IC co-packaged with a power transistor such as an IGBT or MOSFET includes a first branch formed by a capacitor and a parallel branch formed by a resistor and a capacitor in series. The circuit, which is part of the IC, is connected between a power supply node and the circuit ground and, at frequencies associated with the noise, exhibits low impedance to the ground, and a high impedance to the IC and the transistor.
US Patent 07167043 Decoupling circuit for co-packaged semiconductor devices US Patent 7167043 Decoupling circuit for co-packaged semiconductor devices
US Patent 07167043 Decoupling circuit for co-packaged semiconductor devices
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