US Patent 6938061 Parallel counter and a multiplication logic circuit
Patent 6938061 was granted and assigned to Arithmatica on August, 2005 by the United States Patent and Trademark Office.
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Patent abstract
A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinatins of each bit of a binary number with each other bit of another binary number is generated having a reduced from in order to reduce the steps required in array reduction.
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Patent Inventor Names
Dmitriy Rumynin0
Peter Meulemans0
Sunil Talwar0
Date of Patent
August 30, 2005
0Patent Application Number
096375320
Date Filed
August 11, 2000
0Patent Primary Examiner
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US Patent 6938061 Parallel counter and a multiplication logic circuit
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