‌

US Patent 6938061 Parallel counter and a multiplication logic circuit

Patent 6938061 was granted and assigned to Arithmatica on August, 2005 by the United States Patent and Trademark Office.

Overview Structured Data Issues Contributors

Is a

1

Patent attributes

Patent Applicant

Loading...

1

Current Assignee

1

Patent Jurisdiction

United States Patent and Trademark Office

1

Patent Number

Patent Inventor Names

Dmitriy Rumynin1

Peter Meulemans1

Sunil Talwar1

Date of Patent

August 30, 2005

1

Patent Application Number

096375321

Date Filed

August 11, 2000

1

Patent Citations Received

US Patent 11838118 Device, system, and method of detecting vishing attacks

2

Patent Primary Examiner

1

Patent abstract

A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinatins of each bit of a binary number with each other bit of another binary number is generated having a reduced from in order to reduce the steps required in array reduction.

Timeline

No Timeline data yet.

Further Resources

Title

Author

Link

Type

Date

No Further Resources data yet.

References

Find more entities like US Patent 6938061 Parallel counter and a multiplication logic circuit

Use the Golden Query Tool to find similar entities by any field in the Knowledge Graph, including industry, location, and more.

Open Query Tool

Golden Query Tool

By using this site, you agree to our Terms of Service.