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US Patent 12068745 Multi-bit scan chain with error-bit generator

Patent 12068745 was granted and assigned to ARM (Asset & Resource Management Holding Company) on August, 2024 by the United States Patent and Trademark Office.

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 US Patent 12068745 Multi-bit scan chain with error-bit generator

Article

Patent abstract

Various implementations described herein are directed to a device having a scan chain that receives a multi-bit input, provides a multi-bit output, and provides a multi-bit multiplexer output based on the multi-bit input and the multi-bit output. The device may have an error-bit generator that receives the multi-bit multiplexer output, receives a portion of the multi-bit input, receives a portion of the multi-bit output, and provides an error-bit output based on the multi-bit multiplexer output, the portion of the multi-bit input, and the portion of the multi-bit output.

Infobox
Is a
Patent
Patent
0
Patent Applicant
ARM (Asset & Resource Management Holding Company)
ARM (Asset & Resource Management Holding Company)
0
Current Assignee
ARM (Asset & Resource Management Holding Company)
ARM (Asset & Resource Management Holding Company)
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
120687450
Patent Inventor Names
Anil Kumar Baratam0
Yves Thomas Laplanche0
Date of Patent
August 20, 2024
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Patent Application Number
174625240
Date Filed
August 31, 2021
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Patent Citations
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US Patent 11088682 High speed digital phase interpolator with duty cycle correction circuitry
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US Patent 8629548 Clock network fishbone architecture for a structured ASIC manufactured on a 28 NM CMOS process lithographic node
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US Patent 8775839 Global hardware supervised power transition management circuits, processes and systems
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US Patent 9261561 Scan chain latch design that improves testability of integrated circuits
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US Patent 9366725 Multiplexer circuit
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US Patent 9444496 Correctable parity protected memory
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US Patent 9543016 Low power high speed program method for multi-time programmable memory device
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US Patent 11221929 Data stream fault detection mechanism in an artificial neural network processor
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US Patent 10204674 Activation of memory core circuits in an integrated circuit
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US Patent 10727854 Apparatus and methods for realization of N time interleaved digital-to-analog converters
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US Patent 10915471 Apparatuses, methods, and systems for memory interface circuit allocation in a configurable spatial accelerator
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Patent Primary Examiner
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Melvin H Pollack
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CPC Code
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H03K 19/1737
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H03K 19/096
0
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H03K 19/0075
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