Patent attributes
A self-test mechanism within an integrated circuit to automatically interleave evaluation of a clock signal by a clock monitor unit with periodic testing for faulty operation of a clock monitor unit implemented within the integrated circuit for monitoring a clock signal. The mechanism injects faults into the clock monitor unit to evaluate if the clock monitor unit is operating in accordance with its specified operating parameters. The injected faults are intended to cause the clock monitor unit to determine that the clock signal is operating outside of a specified frequency range. If the injected faults do not cause the clock monitor unit to determine that the clock signal is operating both above and below the specified frequency range, then the clock monitor unit is not functioning according to specified operating parameters.
