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US Patent 11935621 Calibration circuit, memory and calibration method

Patent 11935621 was granted and assigned to ChangXin Memory Technologies on March, 2024 by the United States Patent and Trademark Office.

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Patent abstractTimelineTable: Further ResourcesReferences
Is a
Patent
Patent
1

Patent attributes

Patent Applicant
ChangXin Memory Technologies
ChangXin Memory Technologies
1
Current Assignee
ChangXin Memory Technologies
ChangXin Memory Technologies
1
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
1
Patent Number
119356211
Patent Inventor Names
Yuxia Wang1
Kai Tian1
Date of Patent
March 19, 2024
1
Patent Application Number
174480511
Date Filed
September 19, 2021
1
Patent Citations
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US Patent 8154352 Oscillating circuit
1
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US Patent 9030244 Clock duty cycle calibration circuitry
1
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US Patent 9252753 Quadrature output ring oscillator and method thereof
1
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US Patent 9270256 Duty cycle correction circuit
1
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US Patent 9667252 Duty cycle correction circuit and duty cycle correction method
1
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US Patent 9985619 Duty cycle corrector, semiconductor device including the same, and method of operating duty cycle corrector
1
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US Patent 9998125 Clock calibration using asynchronous digital sampling
1
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US Patent 10241537 Digital on-chip duty cycle monitoring device
1
...
Patent Primary Examiner
‌
Jeffrey S Zweizig
1
Patent abstract

A calibration circuit includes: a differential input circuit, configured to receive first and second oscillation signals, the first and second oscillation signals having the same frequency and opposite phases, duty cycle of the first oscillation signal and duty cycle of the second oscillation signal being in a first preset range, and the differential input circuit being configured to output first and internal signals; a comparison unit, connected to an output end of the differential input circuit and configured to compare duty cycle of the first internal signal and/or duty cycle of the second internal signal; and a logical unit, connected to the comparison unit and the differential input circuit, and configured to control the differential input circuit according to an output result of the comparison unit, such that the duty cycle of the first internal signal and/or the duty cycle of the second internal signal reaches a second preset range.

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