US Patent 11189338 Multi-rank high bandwidth memory (HBM) memory

Certain aspects of the present disclosure provide techniques for relate to electronic devices that are configured to implement multi-rank high bandwidth memory (HBM) memory. In one aspect, an electronic device includes a chip that includes an interface circuit. The interface circuit is connected to first exterior pads. The first exterior pads have a first number of first data input/output exterior pads and a second number of clock enable output exterior pads. The first number is a first integer multiple of a number of data signals per channel of high bandwidth memory (HBM), and the second number is a second integer multiple of a number of clock enable signals per channel of the HBM. The second integer multiple is greater than the first integer multiple.