US Patent 11061829 Prefetch support with address space randomization

A system includes a memory, a processor in communication with the memory, an application, and a supervisor. The supervisor is configured to allocate an identifier corresponding to a virtual memory area and expose a data structure that is readable by the application. Responsive to a fault trigger associated with an address, the supervisor is configured to record fault information in the data structure. The application is configured to predict at least a portion of subsequent fault information based on fault information recorded in the data structure.