US Patent 11031909 Group delay optimization circuit and related apparatus

A group delay optimization circuit is provided. The group delay optimization circuit receives a first signal (e.g., a voltage signal) and a second signal (e.g., a current signal). Notably, the first signal and the second signal may experience different group delays that can cause the first signal and the second signal to misalign at an amplifier circuit configured to amplify a radio frequency (RF) signal. The group delay optimization circuit is configured to determine a statistical indicator indicative of a group delay offset between the first signal and the second signal. Accordingly, the group delay optimization circuit may minimize the group delay offset by reducing the statistical indicator to below a defined threshold in one or more group delay optimization cycles. As a result, it may be possible to pre-compensate for the group delay offset in the RF signal, thus helping to improve efficiency and linearity of the amplifier circuit.