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US Patent 10535391 Semiconductor storage device

Patent 10535391 was granted and assigned to Toshiba Memory Corporation on January, 2020 by the United States Patent and Trademark Office.

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Patent abstractTimelineTable: Further ResourcesReferences
Is a
Patent
Patent
1

Patent attributes

Patent Applicant
Toshiba Memory Corporation
Toshiba Memory Corporation
1
Current Assignee
Toshiba Memory Corporation
Toshiba Memory Corporation
1
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
1
Patent Number
105353911
Patent Inventor Names
Kosuke Hatsuda1
Yoshiaki Osada1
Date of Patent
January 14, 2020
1
Patent Application Number
161240071
Date Filed
September 6, 2018
1
Patent Citations
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US Patent 10163977 Chalcogenide memory device components and composition
Patent Citations Received
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US Patent 12079733 Multi-precision digital compute-in-memory deep neural network engine for flexible and energy efficient inferencing
4
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US Patent 11508424 Variable resistance memory device
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US Patent 11663471 Compute-in-memory deep neural network inference engine using low-rank approximation technique
7
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US Patent 11328204 Realization of binary neural networks in NAND memory arrays
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US Patent 11397886 Vertical mapping and computing for deep neural networks in non-volatile memory
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US Patent 11397885 Vertical mapping and computing for deep neural networks in non-volatile memory
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US Patent 11495278 Memory device
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US Patent 10643119 Differential non-volatile memory cell for artificial neural network
...
Patent Primary Examiner
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Gene N Auduong
1
Patent abstract

According to one embodiment, a semiconductor storage device includes: a first conductor coupled to a first end of a first cell; a second conductor which couples between a second end of the first cell and a first end of a second cell; a third conductor coupled to a second end of the second cell; a first current source being capable of coupling to the first cell via the first conductor; a second current source being capable of coupling to the second cell via the third conductor; a first sense amplifier configured to read data from the first cell based on a current flowing from the first current source to the first cell; and a second sense amplifier configured to read data from the second cell based on a current flowing from the second cell to the second current source.

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