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US Patent 7157937 Structured integrated circuit device

Patent 7157937 was granted and assigned to EASIC on January, 2007 by the United States Patent and Trademark Office.

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Patent
Patent

Patent attributes

Current Assignee
EASIC
EASIC
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
7157937
Date of Patent
January 2, 2007
Patent Application Number
11186923
Date Filed
July 22, 2005
Patent Citations Received
‌
US Patent 12136562 3D semiconductor device and structure with single-crystal layers
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US Patent 12094892 3D micro display device and structure
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US Patent 12120880 3D semiconductor device and structure with logic and memory
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US Patent 12125737 3D semiconductor device and structure with metal layers and memory cells
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US Patent 11694922 Multilevel semiconductor device and structure with oxide bonding
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US Patent 11694944 3D semiconductor device and structure with metal layers and a connective path
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US Patent 11711928 3D memory devices and structures with control circuits
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US Patent 11763864 3D memory semiconductor devices and structures with bit-line pillars
...
Patent Primary Examiner
‌
Anh Q Tran
Patent abstract

A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

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