Patent attributes
A method for execution by a Dynamic Random Access (DRAM) cell processing circuit, includes charging a bit-line operably coupled to a plurality of DRAM cells of a DRAM memory device, including a current DRAM cell, at a first voltage to pre-charge the parasitic capacitance between ground and the bit-line to a second voltage, where the second voltage is between a logic 1 voltage and a logic 0 voltage. The method continues by sensing a voltage change on the bit-line based on a difference between a voltage stored on a DRAM cell capacitor of the current DRAM cell and the second voltage and outputting a read output voltage that is generated based on the sensed voltage change. The method then continues by supplying, while outputting the read output voltage, the read output voltage to the bit-line to refresh the voltage stored in the DRAM cell capacitor of the current DRAM cell.
