List of LogicVision patents

Patents where

Current Assignee

Name

LogicVision

Name	Description	Current Assignee	Patent Jurisdiction	Patent Number	Date of Patent
‌ US Patent 7139946 Method and test circuit for testing memory internal write enable	Patent 7139946 was granted and assigned to LogicVision on November, 2006 by the United States Patent and Trademark Office.	LogicVision	United States Patent and Trademark Office	7139946	November 21, 2006
‌ US Patent 7370251 Method and circuit for collecting memory failure information	Patent 7370251 was granted and assigned to LogicVision on May, 2008 by the United States Patent and Trademark Office.	LogicVision	United States Patent and Trademark Office	7370251	May 6, 2008
‌ US Patent 7194669 Method and circuit for at-speed testing of scan circuits	Patent 7194669 was granted and assigned to LogicVision on March, 2007 by the United States Patent and Trademark Office.	LogicVision	United States Patent and Trademark Office	7194669	March 20, 2007
‌ US Patent 7103860 Verification of embedded test structures in circuit designs	Patent 7103860 was granted and assigned to LogicVision on September, 2006 by the United States Patent and Trademark Office.	LogicVision	United States Patent and Trademark Office	7103860	September 5, 2006
‌ US Patent 7159159 Circuit and method for adding parametric test capability to digital boundary scan	Patent 7159159 was granted and assigned to LogicVision on January, 2007 by the United States Patent and Trademark Office.	LogicVision	United States Patent and Trademark Office	7159159	January 2, 2007
‌ US Patent 7617425 Method for at-speed testing of memory interface using scan	Patent 7617425 was granted and assigned to LogicVision on November, 2009 by the United States Patent and Trademark Office.	LogicVision	United States Patent and Trademark Office	7617425	November 10, 2009
‌ US Patent 7158899 Circuit and method for measuring jitter of high speed signals	Patent 7158899 was granted and assigned to LogicVision on January, 2007 by the United States Patent and Trademark Office.	LogicVision	United States Patent and Trademark Office	7158899	January 2, 2007
‌ US Patent 7257733 Memory repair circuit and method	Patent 7257733 was granted and assigned to LogicVision on August, 2007 by the United States Patent and Trademark Office.	LogicVision	United States Patent and Trademark Office	7257733	August 14, 2007
‌ US Patent 7424656 Clocking methodology for at-speed testing of scan circuits with synchronous clocks	Patent 7424656 was granted and assigned to LogicVision on September, 2008 by the United States Patent and Trademark Office.	LogicVision	United States Patent and Trademark Office	7424656	September 9, 2008
‌ US Patent 7155651 Clock controller for at-speed testing of scan circuits	Patent 7155651 was granted and assigned to LogicVision on December, 2006 by the United States Patent and Trademark Office.	LogicVision	United States Patent and Trademark Office	7155651	December 26, 2006
‌ US Patent 7191374 Method of and program product for performing gate-level diagnosis of failing vectors	Patent 7191374 was granted and assigned to LogicVision on March, 2007 by the United States Patent and Trademark Office.	LogicVision	United States Patent and Trademark Office	7191374	March 13, 2007
‌ US Patent 7188274 Memory repair analysis method and circuit	Patent 7188274 was granted and assigned to LogicVision on March, 2007 by the United States Patent and Trademark Office.	LogicVision	United States Patent and Trademark Office	7188274	March 6, 2007
‌ US Patent 7219282 Boundary scan with strobed pad driver enable	Patent 7219282 was granted and assigned to LogicVision on May, 2007 by the United States Patent and Trademark Office.	LogicVision	United States Patent and Trademark Office	7219282	May 15, 2007
‌ US Patent 7453255 Circuit and method for measuring delay of high speed signals	Patent 7453255 was granted and assigned to LogicVision on November, 2008 by the United States Patent and Trademark Office.	LogicVision	United States Patent and Trademark Office	7453255	November 18, 2008
‌ US Patent 6862717 Method and program product for designing hierarchical circuit for quiescent current testing	Patent 6862717 was granted and assigned to LogicVision on March, 2005 by the United States Patent and Trademark Office.	LogicVision	United States Patent and Trademark Office	6862717	March 1, 2005
‌ US Patent 6961871 Method, system and program product for testing and/or diagnosing circuits using embedded test controller access data	Patent 6961871 was granted and assigned to LogicVision on November, 2005 by the United States Patent and Trademark Office.	LogicVision	United States Patent and Trademark Office	6961871	November 1, 2005
‌ US Patent 6885213 Circuit and method for accurately applying a voltage to a node of an integrated circuit	Patent 6885213 was granted and assigned to LogicVision on April, 2005 by the United States Patent and Trademark Office.	LogicVision	United States Patent and Trademark Office	6885213	April 26, 2005
‌ US Patent 6868532 Method and program product for designing hierarchical circuit for quiescent current testing and circuit produced thereby	Patent 6868532 was granted and assigned to LogicVision on March, 2005 by the United States Patent and Trademark Office.	LogicVision	United States Patent and Trademark Office	6868532	March 15, 2005
‌ US Patent 6883134 Method and program product for detecting bus conflict and floating bus conditions in circuit designs	Patent 6883134 was granted and assigned to LogicVision on April, 2005 by the United States Patent and Trademark Office.	LogicVision	United States Patent and Trademark Office	6883134	April 19, 2005
‌ US Patent 6895535 Circuit and method for testing high speed data circuits	Patent 6895535 was granted and assigned to LogicVision on May, 2005 by the United States Patent and Trademark Office.	LogicVision	United States Patent and Trademark Office	6895535	May 17, 2005

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