List of Cadence Design Systems patents

Patents where

Current Assignee

Name

Cadence Design Systems

Name	Description	Patent Applicant	Current Assignee	Patent Jurisdiction	Patent Number	Date of Patent
‌ US Patent 7562323 System, method and computer program product for handling small aggressors in signal integrity analysis	Patent 7562323 was granted and assigned to Cadence Design Systems on July, 2009 by the United States Patent and Trademark Office.		Cadence Design Systems	United States Patent and Trademark Office	7562323	July 14, 2009
‌ US Patent 11531803 IPBA-driven full-depth EPBA of operational timing for circuit design	Patent 11531803 was granted and assigned to Cadence Design Systems on December, 2022 by the United States Patent and Trademark Office.	Cadence Design Systems	Cadence Design Systems	United States Patent and Trademark Office	11531803	December 20, 2022
‌ US Patent 11429776 Fault rules files for testing an IC chip	Patent 11429776 was granted and assigned to Cadence Design Systems on August, 2022 by the United States Patent and Trademark Office.	Cadence Design Systems	Cadence Design Systems	United States Patent and Trademark Office	11429776	August 30, 2022
‌ US Patent 7292968 Hot carrier circuit reliability simulation	Patent 7292968 was granted and assigned to Cadence Design Systems on November, 2007 by the United States Patent and Trademark Office.		Cadence Design Systems	United States Patent and Trademark Office	7292968	November 6, 2007
‌ US Patent 7353467 Method and system for facilitating electronic circuit and chip design using remotely located resources	Patent 7353467 was granted and assigned to Cadence Design Systems on April, 2008 by the United States Patent and Trademark Office.		Cadence Design Systems	United States Patent and Trademark Office	7353467	April 1, 2008
‌ US Patent 7337421 Method and system for managing design corrections for optical and process effects based on feature tolerances	Patent 7337421 was granted and assigned to Cadence Design Systems on February, 2008 by the United States Patent and Trademark Office.		Cadence Design Systems	United States Patent and Trademark Office	7337421	February 26, 2008
‌ US Patent 7349493 Demodulation with separate branches for phase and amplitude	Patent 7349493 was granted and assigned to Cadence Design Systems on March, 2008 by the United States Patent and Trademark Office.		Cadence Design Systems	United States Patent and Trademark Office	7349493	March 25, 2008
‌ US Patent 7093259 Hierarchically structured logging for computer work processing	Patent 7093259 was granted and assigned to Cadence Design Systems on August, 2006 by the United States Patent and Trademark Office.		Cadence Design Systems	United States Patent and Trademark Office	7093259	August 15, 2006
‌ US Patent 6971076 Method for estimating peak crosstalk noise based on separate crosstalk model	Patent 6971076 was granted and assigned to Cadence Design Systems on November, 2005 by the United States Patent and Trademark Office.		Cadence Design Systems	United States Patent and Trademark Office	6971076	November 29, 2005
‌ US Patent 7197738 Method and apparatus for routing	Patent 7197738 was granted and assigned to Cadence Design Systems on March, 2007 by the United States Patent and Trademark Office.		Cadence Design Systems	United States Patent and Trademark Office	7197738	March 27, 2007
‌ US Patent 7774735 Integrated circuit netlist migration	Patent 7774735 was granted and assigned to Cadence Design Systems on August, 2010 by the United States Patent and Trademark Office.		Cadence Design Systems	United States Patent and Trademark Office	7774735	August 10, 2010
‌ US Patent 6907591 Method and apparatus for performing extraction using a neural network	Patent 6907591 was granted and assigned to Cadence Design Systems on June, 2005 by the United States Patent and Trademark Office.		Cadence Design Systems	United States Patent and Trademark Office	6907591	June 14, 2005
‌ US Patent 7024652 System and method for adaptive partitioning of circuit components during simulation	Patent 7024652 was granted and assigned to Cadence Design Systems on April, 2006 by the United States Patent and Trademark Office.		Cadence Design Systems	United States Patent and Trademark Office	7024652	April 4, 2006
‌ US Patent 7143021 Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure	Patent 7143021 was granted and assigned to Cadence Design Systems on November, 2006 by the United States Patent and Trademark Office.		Cadence Design Systems	United States Patent and Trademark Office	7143021	November 28, 2006
‌ US Patent 7567891 Hot-carrier device degradation modeling and extraction methodologies	Patent 7567891 was granted and assigned to Cadence Design Systems on July, 2009 by the United States Patent and Trademark Office.		Cadence Design Systems	United States Patent and Trademark Office	7567891	July 28, 2009
‌ US Patent 10909283 Hardware assisted weighted toggle count	Patent 10909283 was granted and assigned to Cadence Design Systems on February, 2021 by the United States Patent and Trademark Office.	Cadence Design Systems	Cadence Design Systems	United States Patent and Trademark Office	10909283	February 2, 2021
‌ US Patent 8365103 System and method for implementing image-based design rules	Patent 8365103 was granted and assigned to Cadence Design Systems on January, 2013 by the United States Patent and Trademark Office.		Cadence Design Systems	United States Patent and Trademark Office	8365103	January 29, 2013
‌ US Patent 8151227 Method and apparatus for pre-tabulating sub-networks	Patent 8151227 was granted and assigned to Cadence Design Systems on April, 2012 by the United States Patent and Trademark Office.		Cadence Design Systems	United States Patent and Trademark Office	8151227	April 3, 2012
‌ US Patent 7310793 Interconnect lines with non-rectilinear terminations	Patent 7310793 was granted and assigned to Cadence Design Systems on December, 2007 by the United States Patent and Trademark Office.		Cadence Design Systems	United States Patent and Trademark Office	7310793	December 18, 2007
‌ US Patent 7383524 Structure for storing a plurality of sub-networks	Patent 7383524 was granted and assigned to Cadence Design Systems on June, 2008 by the United States Patent and Trademark Office.		Cadence Design Systems	United States Patent and Trademark Office	7383524	June 3, 2008
‌ US Patent 11775723 Methods, systems, and computer program products for efficiently implementing a 3D-IC	Patent 11775723 was granted and assigned to Cadence Design Systems on October, 2023 by the United States Patent and Trademark Office.	Cadence Design Systems	Cadence Design Systems	United States Patent and Trademark Office	11775723	October 3, 2023
‌ US Patent 7584441 Method for generating optimized constraint systems for retimable digital designs	Patent 7584441 was granted and assigned to Cadence Design Systems on September, 2009 by the United States Patent and Trademark Office.		Cadence Design Systems	United States Patent and Trademark Office	7584441	September 1, 2009
‌ US Patent 7779381 Test generation for low power circuits	Patent 7779381 was granted and assigned to Cadence Design Systems on August, 2010 by the United States Patent and Trademark Office.		Cadence Design Systems	United States Patent and Trademark Office	7779381	August 17, 2010
‌ US Patent 8380468 Methods for facilitating specification allocation of hierarchical systems	Patent 8380468 was granted and assigned to Cadence Design Systems on February, 2013 by the United States Patent and Trademark Office.		Cadence Design Systems	United States Patent and Trademark Office	8380468	February 19, 2013
‌ US Patent 9026978 Reverse interface logic model for optimizing physical hierarchy under full chip constraint	Patent 9026978 was granted and assigned to Cadence Design Systems on May, 2015 by the United States Patent and Trademark Office.	Cadence Design Systems	Cadence Design Systems	United States Patent and Trademark Office	9026978	May 5, 2015

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