US Patent 9851905 Concurrent memory operations for read operation preemption

A non-volatile memory interface employs concurrent memory operations for read operation preemption and includes transaction control logic configured to resume a suspended write operation concurrently with at least a portion of the transfer of read data from a non-volatile memory for a read operation which preempted the write operation. Memory control logic of the memory interface is configured to issue to the write operation suspend logic, a write operation resume command. The transaction control logic may be further configured to automatically suspend performing of a write operation in response to receipt of a read command. The transaction control logic may also be configured to automatically resume a previously suspended write operation in response to completion of a preemptive read operation by the memory.