US Patent 9548121 Memory device having only the top poly cut

Methods and apparatuses are contemplated herein for enhancing the efficiency of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a substrate and 3D array of nonvolatile memory cells, the 3D array including a plurality of conductive layers, separated from each other by insulating layers, the plurality of conductive layers comprising a top layer, the top layer comprising n string select lines (SSLs) and one or more bottom layers, the top layer further comprises n−1 cuts, each cut electrically separating two SSLs, wherein each cut is cut to a depth of the top layer and not extending into the bottom layers and a plurality of vertical channels arranged orthogonal to the plurality of layers, each of the plurality of channels comprising a string of memory cells, each of plurality of strings coupled to a bit line, an SSL and one or more word lines.