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US Patent 7943406 LED fabrication via ion implant isolation

Patent 7943406 was granted and assigned to Wolfspeed on May, 2011 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
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Patent attributes

Current Assignee
Wolfspeed
Wolfspeed
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
79434060
Patent Inventor Names
Alexander Suvorov0
David Beardsley Slater, Jr.0
Iain Hamilton0
John Adam Edmond0
Date of Patent
May 17, 2011
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Patent Application Number
123278820
Date Filed
December 4, 2008
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Patent Citations Received
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US Patent 11923402 Light emitting diode device
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US Patent 11961875 Monolithic segmented LED array architecture with islanded epitaxial growth
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US Patent 11955583 Flip chip micro light emitting diodes
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US Patent 11705534 Methods of making flip chip micro light emitting diodes
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US Patent 11942507 Light emitting diode devices
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US Patent 11784286 Light emitting diode devices with defined hard mask opening
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US Patent 11777061 Light emitting diode device with tunable emission
Patent Primary Examiner
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Kevin M. Picardat
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Patent abstract

A semiconductor light emitting diode includes a semiconductor substrate, an epitaxial layer of n-type Group III nitride on the substrate, a p-type epitaxial layer of Group III nitride on the n-type epitaxial layer and forming a p-n junction with the n-type layer, and a resistive gallium nitride region on the n-type epitaxial layer and adjacent the p-type epitaxial layer for electrically isolating portions of the p-n junction. A metal contact layer is formed on the p-type epitaxial layer. Some embodiments include a semiconductor substrate, an epitaxial layer of n-type Group III nitride on the substrate, a p-type epitaxial layer of Group III nitride on the n-type epitaxial layer and forming a p-n junction with the n-type layer, wherein portions of the epitaxial region are patterned into a mesa and wherein the sidewalls of the mesa comprise a resistive Group III nitride region for electrically isolating portions of the p-n junction. In method embodiments disclosed, the resistive border is formed by forming an implant mask on the p-type epitaxial region and implanting ions into portions of the p-type epitaxial region to render portions of the p-type epitaxial region semi-insulating. A photoresist mask or a sufficiently thick metal layer may be used as the implant mask. In some method embodiments, a mesa is formed in the epitaxial region prior to implantation. During implantation, the epiwafer is mounted at an angle such that ions are implanted directly into the sidewalls of the mesa, thereby rendering portions of the mesa semi-insulating. The epiwafer may be rotated during ion implantation.

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