Patent attributes
In a single data rate (SDR) mode, logic level transitions of a data condition prior-determination signal RDYO are outputted to an output terminal (O) in response to an internal clock signal CKI. A ready signal RDY is outputted in synchronization with the internal clock signal CKI following a logic level transition of the data condition prior-determination signal RDYO. In a double data rate (DDR) mode, on the other hand, a toggle signal is outputted to the output terminal (O) in correspondence with the internal clock signal CKI following a logical level transition of the data condition prior-determination signal RDYO. After the internal clock signal CKI following the logical level transition of the data condition prior-determination signal RDYO, a strobe signal DQS is outputted in synchronization with the internal clock signal CKI. The ready signal RDY is outputted at the data condition informing terminal (X) in SDR mode while, on the other hand, the strobe signal DQS is outputted at the data condition informing terminal (X) in DDR mode.
