Patent attributes
A power module includes a power semiconductor device having a first terminal, a second terminal, and a third terminal. The second terminal is a control terminal to regulate flow of electricity between the first and third terminals. A gate driver has an output node coupled to the second terminal of the power device. The gate driver includes an upper transistor and a lower transistor provided in a half-bridge configuration. The output node of the gate driver is provided between the upper and lower transistors. A first delay circuit is coupled to a control terminal of the upper transistor to provide a first delay period for a first gate drive signal being applied to the control terminal of the upper transistor. A second delay circuit is coupled to a control terminal of the lower transistor to provide a second delay period for a second gate drive signal being applied to the control terminal the lower transistor. The first delay period is different from the second delay period.
