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US Patent 12137140 Scale out storage platform having active failover

Patent 12137140 was granted and assigned to Pure Storage on November, 2024 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent
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Patent attributes

Patent Applicant
Pure Storage
Pure Storage
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Current Assignee
Pure Storage
Pure Storage
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
121371400
Patent Inventor Names
Taras Glek0
Jayesh Patel0
Prabhath Sajeepa0
Date of Patent
November 5, 2024
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Patent Application Number
171476390
Date Filed
January 13, 2021
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Patent Citations
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US Patent 7065617 Efficient write-watch mechanism useful for garbage collection in a computer system
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US Patent 7076606 Accelerated RAID with rewind capability
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US Patent 7107480 System and method for preventing data corruption in solid-state memory devices after a power failure
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US Patent 7159150 Distributed storage system capable of restoring data in case of a storage failure
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US Patent 7162575 Adaptive implementation of requested capabilities for a logical volume
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US Patent 7164608 NVRAM memory cell architecture that integrates conventional SRAM and flash cells
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US Patent 7188270 Method and system for a disk fault tolerance in a disk array using rotating parity
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US Patent 7334156 Method and apparatus for RAID conversion
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...
Patent Primary Examiner
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Jonathan A Bui
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CPC Code
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H04L 41/0668
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H04L 45/22
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H04L 45/245
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H04L 2012/5627
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H04L 41/0663
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H04L 49/15
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Patent abstract

A storage system that has blades and fabric modules connects to a customer legacy network that has a first, active switch and a second, passive switch. A first link aggregation group (LAG) is configured active and includes ports of the first, active switch that connect via links to the first and second fabric modules of the storage system. A second LAG is configured passive and includes ports of the second, passive switch that connect via links to the first and second fabric modules. A multi-chassis link aggregation group (MLAG, MCLAG or MC-LAG) is configured and includes ports of the first and second fabric modules that connect via links to the first and second switches.

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